• Microelectronics
  • Vol. 53, Issue 5, 772 (2023)
XIAO Yuan, LIANG Huaguo, WANG Yuchuan, LU Yingchun, YI Maoxiang, and YAO Liang
Author Affiliations
  • [in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.220510 Cite this Article
    XIAO Yuan, LIANG Huaguo, WANG Yuchuan, LU Yingchun, YI Maoxiang, YAO Liang. Design of a Nonlinear Optimized Time to Digital Converter[J]. Microelectronics, 2023, 53(5): 772 Copy Citation Text show less
    References

    [1] MIYASE K, ASO M, OOTSUKA R, et al. A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits [C]// 2012 IEEE 30th VLSI Test Symposium (VTS). Maui, HI, USA. 2012: 197-202.

    [3] SEO H, YOON H, KIM D, et al. Direct TOF scanning LiDAR sensor with two-step multievent histogramming TDC and embedded interference filter [J]. IEEE Journal of Solid-State Circuits, 2021, 56(4): 1022-1035.

    [5] WON J Y, KWON S I, YOON H S, et al. Dual-phase tapped-delay-line time-to-digital converter with on-the-fly calibration implemented in 40 nm FPGA [J]. IEEE Transactions on Biomedical Circuits and Systems, 2015, 10(1): 231-242.

    [6] WU J, SHI Z. The 10-ps wave union TDC: improving FPGA TDC resolution beyond its cell delay [C]// 2008 IEEE Nuclear Science Symposium Conference. Dresden, Germany. 2008: 3440-3446.

    [7] WANG Y, LIU C. A nonlinearity minimization-oriented resource-saving time-to-digital converter implemented in a 28 nm Xilinx FPGA [J]. IEEE Transactions on Nuclear Science, 2015, 62(5): 2003-2009.

    [8] SHEN Q, LIU S, QI B, et al. A 1.7 ps equivalent bin size and 4.2 ps RMS FPGA TDC based on multichain measurements averaging method [J]. IEEE Transactions on Nuclear Science, 2015, 62(3): 947-954.

    [9] KORKAN A O, YUKSEL H. A novel time-to-amplitude converter and a low-cost wide dynamic range FPGA TDC for LiDAR application [J]. IEEE Transactions on Instrumentation and Measurement, 2022, 71: 1-15.

    [11] KALISZ J. Review of methods for time interval measurements with picosecond resolution [J]. Metrologia, 2003, 41(1): 17-32.

    [12] PARSAKORDASIABI M, VORNICU I, RODRGUEZ-VZQUEZ, et al. An efficient TDC using a dual-mode resource-saving method evaluated in a 28-nm FPGA [J]. IEEE Transactions on Instrumentation and Measurement, 2022, 71: 1-13.

    [13] WON J Y, KWON S I, YOON H S, et al. Dual-phase tapped-delay-line time-to-digital converter with on-the-fly calibration implemented in 40 nm FPGA [J]. IEEE Transactions on Biomedical Circuits and Systems, 2015, 10(1): 231-242.

    [15] WU J. Several key issues on implementing delay line based TDCs using FPGAs [J]. IEEE Transactions on Nuclear Science, 2010, 57(3): 1543-1548.

    [17] XU G, ZHA B, XIA T, et al. A high-throughput Vernier time-to-digital converter on FPGAs with improved resolution using a bi-time interpolation scheme [J]. Applied Sciences, 2022, 12(15): 7674.

    XIAO Yuan, LIANG Huaguo, WANG Yuchuan, LU Yingchun, YI Maoxiang, YAO Liang. Design of a Nonlinear Optimized Time to Digital Converter[J]. Microelectronics, 2023, 53(5): 772
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