The poor nonlinearity of the tapped delay chain cascaded by Carry4 units in FPGA is one of the important problems to be solved in TDC measurement system. Based on the existing tapped sampling sequence (" SCSC "), a method of "mixed" tapped sampling sequence was proposed to solve this problem, and the non-uniformity of delay units was significantly improved. The built TDC consisted of modules such as tapped delay chain, sampling and coding logic circuit, and code density calibration, and was verified on a Xilinx Kintex-7 series chip. The experimental results show that the differential nonlinearity of this method is reduced by 32.0% and the integral nonlinearity is reduced by 22.8% compared with that of the "SCSC" sequence. Through further calibration, the achieved resolution (LSB) of TDC is 13.51 ps, the measurement accuracy is 19.17 ps, the differential nonlinearity range is ［-0.45,0.96］LSB, and the integral nonlinearity range is ［-3.27,1.33］LSB.