With the increasing demand for high-speed sampling technology, photonic analog-to-digital converter (PADC) technology is regarded as an ideal solution that can overcome the bottleneck faced by electronic analog-to-digital converters (EADCs)^[1–4]. To achieve an ultra-high sampling rate with high resolution, one of the most feasible PADC schemes is proposed, consisting of a photonic sampling front-end and an electronic digitization back-end^[5,6]. In terms of the channel-interleaved PADC^[7], many breakthroughs have been made in recent years^[8–16]. Most of all, a previous research has demonstrated the application of a time-domain channel-interleaved demultiplexer in a high-speed PADC, which converts sampling series of 20 GSa/s into two parallel channels of 10 GSa/s^[17]. This scheme is constructed by an array of photonic switches that are driven by RF signals. The characteristics of the RF signals are crucial to the performance of photonic switches as well as the demultiplexer^[18]. However, multiple RF components separately packaged in modules result in bulkiness, high cost, and large power consumption, even when there are only two demultiplexed channels^[17].

On the other hand, the technology of RF modules with a single or multichip is mature^[19,20]. Passive and active elements can be integrated in organic laminates or low temperature co-fired ceramic (LTCC) substrates. In the multichip module, internal separating walls between cavities distribute the gain and isolate the cavities with minimum parasitic effects on chip parameters. Microstrip lines and gold wires are the main methods of connecting different chips. In this way, we can connect amplifiers and filters without microwave cables, which bring about large power loss and instability. Based on this situation, we design a compact RF module, which supports more demultiplexed channels to satisfy the requirement in practical applications of PADC.

In this Letter, we analyze the relationship between the characteristics of RF driver signals and the performance of a time-domain channel-interleaved demultiplexer based on photonic switches. The optical signal-to-distortion ratio (OSDR) is regarded as the most effective parameter to evaluate the demultiplexer performance. A multi-frequency RF driver is designed for the optimization of the OSDR in the PADC system. In our design, low noise amplifiers (LNAs), power amplifiers (PAs), variable attenuators (VAs), and variable phase shifters (VPSs) are cascaded to obtain sufficient gain and well-managed amplitude and phase. Then, the RF driver is applied in an eight-channel PADC system with a sampling rate of 40 GSa/s. The performance is verified in the demultiplexer of the sampling series.

A schematic of an eight-channel 40 GSa/s PADC system with a channel-interleaved demultiplexer based on photonic switches is illustrated in Fig. 1. In this scheme, an actively mode locked laser (AMLL) with a high repetition rate serves as a photonic sampling clock generator, and a Mach–Zehnder modulator (MZM) is used as a sampling gate. For the demultiplexer, an array of dual-output MZMs (DOMZMs) is applied as the photonic switches. The demultiplexed series are detected via photodiodes (PDs) and then digitized by EADCs for digital processing.

The topological structure of the demultiplexer can be considered as a binary tree of DOMZMs. In this structure, two DOMZMs are connected to each output port of the DOMZM in the previous class. A three-class cascaded scheme is shown in the inset of Fig. 1, which can convert the sampling series of 40 GSa/s into eight parallel channels with the speed of 5 GSa/s. In the channel-interleaved demultiplexer, the DOMZM in the first class is driven by an RF signal of 20 GHz, and the frequencies of the driver signals are 10 GHz and 5 GHz for the second and third classes, respectively.

The parameters of each RF signal should be properly managed. In mathematics, the conclusion in Ref. [17] can be extended to multi-channel cases. As for a demultiplexer consisting of multiple classes of DOMZMs, the switching response of one DOMZM in the Kth class can be expressed as αK(t)=(αmax,K−αmin,K)[1+ηK(t)]/2+αmin,K,(1)where K=1, 2, 3, and αmax,K and αmin,K are the maximum and minimum transmittances of the DOMZM. ηK(t) is demultiplexing modulation determined by the RF driver signal, which can be derived as ηK(t)=sin[π(VK/Vπ,K)cos(2πt/2KTS+φK)],(2)where VK and φK are the amplitude and phase offsets of the applied driver signal in the Kth class, respectively. TS is the temporal period of the photonic sampling clock, and Vπ,K is the AC half-wave voltage of the Kth-class DOMZM, which operates with DC quadrature bias. According to Ref. [17], the waveform of the driver signal should remain sinusoidal, and its amplitude should not exceed Vπ,K/2 to avoid unexpected distortion.

In a three-class DOMZM-based demultiplexer, one of the demultiplexed series from the output of Kth-class DOMZM can be expressed as sdemux(t)=sori(t)∏K≤L3αL(t),(3)where sdemux(t) and sori(t) are the demultiplexed series and the original input series before demultiplexing, respectively. As shown in Eq. (3), the original input series is time-interleaved into eight parallel channels after three-class switching, as depicted in Fig. 2(a). In one period (i.e., 8TS) of each demultiplexed channel, a sampling pulse is selected to pass while the rest is suppressed by the switching response in Eq. (1). Assume that the maximums of each αK(t) are temporally aligned at t=0 with the sampling pulse selected to pass. Using Eqs. (1)–(3), the intensity of the selected pulse after the Kth-class DOMZM can be derived as IS=I0∏L≤K3α+,L,(4)where I0 is the intensity of the original sampling series. IS is the intensity of the selected pulse and α+,K=αK (t=0). As shown in Fig. 2(a), there are several remnants, which are considered as distortions, in the suppressed pulses after demultiplexing. The intensity can also be evaluated by Eqs. (1)–(3) as follows: ID,K=I0∏L<K3α+,L×α−,K,(5)where ID,K (K=1, 2, 3) represents the intensity of the distortions, which are marked in Fig. 2(a) and measured from the output of the Kth-class DOMZM, and α−,K=αK(t=2K−1TS). Based on Eqs. (4) and (5), the demultiplexing performance of the Kth-class DOMZM could be evaluated by the ratio between the intensity of the selected pulse and distortions. It is a specific OSDR measured at the output of the Kth-class DOMZM as OSDRK=IS/ID,K=α+,K/α−,K,(6)where IS and ID,K are defined by Eqs. (4) and (5), respectively. With the expression in Eq. (6), the OSDR of the final demultiplexed series after three-class DOMZMs can be calculated by Eqs. (3)–(5) as follows: OSDR={∑K=13[∏L>K3(αmax,L/α+,L)×OSDRK−1]}−1.(7)

According to Eqs. (6) and (7), to achieve an optimized OSDR, each OSDRK should be maximized. Since αmax,K and αmin,K are inherent characteristics of DOMZMs, the demultiplexing modulation ηK(t=0) in Eq. (2) should be maximized in each class. It is obvious that the ideal condition can achieve the maximum OSDR, which is ηK(t=0)=1, corresponding to VK=Vπ,K/2 and φK=0.

To investigate the effect of the parameters of RF driver signals, their amplitude and phase can be normalized as ΔVK=0.5−VK/Vπ,K,ΔφK=0−φK,(8)where ΔVK and ΔφK represent the offsets of VK and φK from the ideal condition (i.e., VK=Vπ,K/2 and φK=0), respectively. There ΔVK=0 and ΔφK=0 in the ideal condition, where ηK=1. Figure 2(b) shows a numerical result of OSDRK versus ΔVK and ΔφK with a preset maximum of 30 dB. It indicates that OSDRK is closer to maximum when the offsets are smaller. In this sense, the amplitude and phase of the RF driver signals must be properly managed to optimize the demultiplexing performance.

As for the demultiplexer, a DOMZM (EOSpace AX-1x2-0MSS-40) of 40 GHz is used as the photonic switch working at 20 GHz in the first class. In the second class, two DOMZMs (EOSpace AX-1x2-0MSS-10) of 10 GHz working at 10 GHz are applied. In the third class, four DOMZMs (EOSpace AX-1x2-0MSS-10) of 10 GHz working at 5 GHz are adopted. According to the transmission curve of the DOMZMs, the AC half-wave voltages for each class are measured to be 5.8 V at 20 GHz, 5.1 V at 10 GHz, and 4.3 V at 5 GHz, respectively. The half-wave voltages are determined by the maximum and minimum output intensities of each DOMZM. As the match impedance is R=50Ω, the power at ΔVK=0 in Eq. (8) should be Vπ,K2/4R, namely 19.3 dBm for the signal of 20 GHz in the first class, 18.2 dBm for each signal of 10 GHz in the second class, and 16.7 dBm for each signal of 5 GHz in the third class. As for the phase offset, the ideal condition ΔφK=0 can be determined by the intensity of the pulse, which is selected to pass and reaches its maximum. In practice, the channel-interleaved demultiplexer is not the only component that requires RF signals in the PADC system, as illustrated in Fig. 1. The AMLL should be seeded to generate the photonic sampling clock at 40 GHz. The EADCs should be triggered to perform the digitization at 5 GHz. All RF signals should be synchronized for coherence.

According to the requirements of RF signals, we design a microwave chain using commercial chips, as shown in Fig. 3(a). In this scheme, the chain adopts a signal of 20 GHz with a power of 0 dBm as the original input, which is divided into four paths by two-class cascaded 1×2 power splitters (PSs). For the first path, through an LNA (WFD180240-L17) and a frequency multiplier (FM, WBD220440-B2), a signal of 40 GHz with a maximum power of 14 dBm is achieved to seed the AMLL. The signal in the second path is directly amplified to 6 dBm by an LNA (WFD180240-L17) and then reaches the maximum power at 25 dBm by a PA (WFD196220-P25). It is used as the driver signal of 20 GHz in the first class. The frequency of the signal in the third path is first divided into 10 GHz by a frequency divider (FD, HMC492LP3). The signal is amplified to 18 dBm by an LNA (WFD060180-L18) and split into two outputs by a 1×2 PS (microstrip line), which is further amplified to 24 dBm in the maximum by PAs (WFD080120-P24) to drive the DOMZMs in the second class. As for the fourth path, the frequency of the signal is divided into 5 GHz by an FD (HMC493LP3). The signal splits into five outputs. Among them, four are amplified to 20 dBm in the maximum by LNAs (WFD020060-L10) and PAs (WFD020060-P26) in sequence for the DOMZMs in the third class, and one is amplified to 10 dBm by an LNA (WFD020060-L10) to serve as the trigger clock for the EADCs. Besides, all the output signals are filtered via band-pass filters (BPF), VAs, and VPSs, to guarantee good waveform and precise adjustment of both amplitude and phase of the output signals.

In implementation, the module includes a front board for RF components and a back board for DC bias. The metal box is used to support the boards and guarantee the performance under various conditions. The size of the module is 120mm×205mm×15mm, as shown Fig. 3(b). It should be noted that there are three paths of seed signals of 40 GHz and two paths of the trigger clock at 5 GHz. The redundant outputs are reserved for the synchronization of peripherals in potential applications.

In terms of performance of the RF driver module, the input bandwidth is 18–22 GHz. Figures 4(a)–4(d) show the typical responses of the output ports of the RF driver module with different frequencies, which are measured by a spectrum analyzer (R&S FSW43). By adjusting the VAs, we can obtain different power. The effect in the phase shift can be observed from the results of the demultiplexer. The adjustment precisions in power and phase shifts are 0.5 dB (6 bits) and 5.6° (6 bits), respectively, depending on the specifications of VAs and VPSs. The spectra of generated RF signals after adjustments are measured, as shown in Figs. 4(e)–4(h). From these spectra, it can be found that the amplitudes of these signals can match well with the requirements of the demultiplexer. These spur-free spectra also indicate good sinusoidal temporal waveforms. In this situation, the power consumption of the module is 15.8 W.

The RF driver module is further applied in a 40 GSa/s PADC for laboratory test. In this system, the AMLL (Calmar PSL-40-1 T) is successfully seeded by the RF driver to generate a sampling clock of 40 GSa/s, which is channel-interleaved by the demultiplexer based on three-class DOMZMs. The demultiplexing performance in each class is tested and optimized one by one based on the adjustment of the amplitude and phase of RF driver signals. Figure 5 shows the temporal waveforms of the demultiplexed series of each class under different conditions of RF driver signals. The waveforms are captured by a sampling oscilloscope (Agilent DCA-X 86100D). Only one channel is illustrated as a representative of each class. It can be found that the series of 40 GSa/s is demultiplexed into series of 20 GSa/s, 10 GSa/s, and 5 GSa/s after each class, respectively. In Figs. 5(a)–5(i), the amplitude and phase offsets of RF driver signals in each class are marked along with the measured waveforms. To evaluate the demultiplexing performance in each class, the OSDRK can be calculated with the measured peak intensity of the pulses in Figs. 5(a)–5(i) according to the definition in Eq. (6). The theoretical estimation can also be derived from Eq. (6) based on the amplitude and phase offsets. Figure 5(j) depicts the OSDRK in each class, which are calculated from the waveforms in Figs. 5(a)–5(i). Note that the maximum and minimum transmittances of DOMZMs are 0.5 dB and 25 dB, respectively. The theoretical estimations are derived from Eq. (6) and compared with the experimentally measured results.

From Fig. 5(j), it can be found that the values of OSDRK increase from ∼5dB to ∼15dB in all three classes along with suppressed amplitude and phase offsets. The feasibility of the theoretical analysis in Eq. (6) can be verified from the consistence between the measured and estimated results. Furthermore, the final demultiplexed 5 GSa/s series under different conditions of amplitude and phase of the RF driver signals applied in each class [i.e., the cases shown in Figs. 5(a)–5(i)] are depicted in Fig. 6. The values of OSDRs are calculated from the waveforms and compared with their estimation derived from Eq. (7) based on the values of OSDRK in each class. A good consistence also verifies the analysis in Eq. (7). In these cases, Fig. 6(a) depicts the temporal waveforms of final demultiplexed series with OSDR1, OSDR2, and OSDR3 according to Figs. 5(a), 5(d), and 5(g), respectively. Similarly, Fig. 6(b) depicts the temporal waveforms of final demultiplexed series according to Figs. 5(b), 5(e), and 5(h). Figure 6(c) depicts the temporal waveforms of the final demultiplexed series according to Figs. 5(c), 5(f), and 5(i). The OSDR of the final demultiplexed series increases with the OSDRK in each class, as shown in Figs. 6(a)–6(c). The best measurable OSDR of the final demultiplexed series after three classes of DOMZMs reaches ∼10dB with a voltage detection precision of ∼17mV. Furthermore, the precision can be further improved by eliminating the noise with ultra-high-speed real-time oscilloscopes through heterodyne detection and the averaging method. Without an EADC, the OSDR is considered as the most effective parameter to evaluate the performance of the demultiplexer. As the OSDR increases, the improvement in the performance of the PADC can be evaluated by the effective number of bits (ENOB). The relationship between the OSDR and the ENOB will be studied in future research.

A microwave-chip-based coherent multi-frequency RF driver module is developed and applied to the channel-interleaved demultiplexer in a PADC system of 40 GSa/s. We theoretically analyze the relationship between the characteristics of generated RF driver signals and demultiplexing performance. In laboratory test, a beam sampling series of 40 GSa/s is converted into eight parallel channels of 5 GSa/s with RF driver signals, which drive the photonic switches. By precisely adjusting the amplitude and phase of these signals, the OSDR is optimized. The results verify the compatibility between the RF driver and the PADC system. With its compact size, the RF driver is considered as one step towards practical application and the next-generation of PADC systems in a module or on a chip.