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    Journals >Microelectronics >Volume 53 >Issue 1 >Page 50 > Article
    • Microelectronics
    • Vol. 53, Issue 1, 50 (2023)
    A Parallel FEC Decoder for JESD204C Protocol
    ZHAO Wenfei1,2, WANG Yonglu2,3, and CHEN Gang2,3
    Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.220026 Cite this Article
    ZHAO Wenfei, WANG Yonglu, CHEN Gang. A Parallel FEC Decoder for JESD204C Protocol[J]. Microelectronics, 2023, 53(1): 50 Copy Citation Text show less
    References

    [6] GANGOPADHYAY D, REYHANI-MASOLEH A. Multiple-bit parity-based concurrent fault detection architecture for parallel CRC computation ［J］. IEEE Trans Comput, 2016. 65(7): 2143-2157.

    [8] LI J, LIU S S, REVIRIEGO, et al. Scheme for periodical concurrent fault detection in parallel CRC circuits ［J］. IET Comput & Digital Tech, 2020, 14(2): 80-85.

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    ZHAO Wenfei, WANG Yonglu, CHEN Gang. A Parallel FEC Decoder for JESD204C Protocol[J]. Microelectronics, 2023, 53(1): 50
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