Based on JESD204C protocol, a parallel FEC decoder for 64B/66B link layer was designed. 64 bit parallel scheme was adopted in it, which reduced the requirement of clock frequency. For the shortened (2074，2048) binary cyclic code in the protocol, a fast rotation circuit was designed. This circuit could be used to reduce the complexity of design. According to the functional verification test of Modelsim, the results show that the decoder can send and receive the data, and correct and report the error. On the Design Compiler platform, TSMC 65 nm standard digital process library is used for logic synthesis. The report shows that when the working frequency of the decoder circuit is 500 MHz, the slack time is 0.10 ns, and the speed of single channel data processing can reach 32 Gbit/s.