• Journal of Semiconductors
  • Vol. 44, Issue 9, 091602 (2023)
Feilian Chen1, Meng Zhang1、*, Yunhao Wan2, Xindi Xu2, Man Wong3, and Hoi-Sing Kwok3
Author Affiliations
  • 1College of Electronic and Information Engineering, Shenzhen University, Shenzhen 518060, China
  • 2Institute of Microscale Optoelectronics (IMO), Shenzhen University, Shenzhen 518060, China
  • 3State Key Laboratory of Advanced Displays and Optoelectronics Technologies, The Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong, China
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    DOI: 10.1088/1674-4926/44/9/091602 Cite this Article
    Feilian Chen, Meng Zhang, Yunhao Wan, Xindi Xu, Man Wong, Hoi-Sing Kwok. Advances in mobility enhancement of ITZO thin-film transistors: a review[J]. Journal of Semiconductors, 2023, 44(9): 091602 Copy Citation Text show less

    Abstract

    Indium-tin-zinc oxide (ITZO) thin-film transistor (TFT) technology holds promise for achieving high mobility and offers significant opportunities for commercialization. This paper provides a review of progress made in improving the mobility of ITZO TFTs. This paper begins by describing the development and current status of metal-oxide TFTs, and then goes on to explain the advantages of selecting ITZO as the TFT channel layer. The evaluation criteria for TFTs are subsequently introduced, and the reasons and significance of enhancing mobility are clarified. This paper then explores the development of high-mobility ITZO TFTs from five perspectives: active layer optimization, gate dielectric optimization, electrode optimization, interface optimization, and device structure optimization. Finally, a summary and outlook of the research field are presented.

    Introduction

    Thin-film transistors (TFTs) are essential components in active matrix (AM) displays because they serve as the switch and drive units for pixels[15]. TFTs, a type of field-effect transistor, have been used for over 80 years[6] and can be categorized into different types based on the material of the active layer. These types include amorphous silicon (a-Si) TFTs[5, 7, 8], polycrystalline silicon (poly-Si) TFTs[2, 912], metal-oxide (MO) TFTs[1316], and organic TFTs[17, 18]. Meanwhile, a-Si TFT has gained widespread usage in the production of large-sized AM liquid crystal displays (LCDs)[1922], primarily due to its low-cost manufacturing process. However, as AM displays move toward higher resolution, the limited mobility of a-Si TFTs is no longer sufficient to meet the requirements[23]. MO TFTs, which can offer improved mobility compared to a-Si TFTs while still maintaining a cost-effective manufacturing process, are gaining significant attention from both industry and academia[2426]. Amorphous indium-gallium-zinc oxide (α-IGZO) TFTs[23, 25] have emerged as the first successful commercialized option among various MO TFTs thanks to their exceptional characteristics, such as high mobility, low leakage current, and steep subthreshold swing. IGZO TFTs are not only utilized in AMLCD panels[24, 25] but are also extensively employed in the drive circuitry of AM light-emitting diode (LED) display panels[26, 27].

    The increasing demand for higher-quality displays has led to the need for more advanced TFT technologies to meet the requirements of AM display panels. At the same time, people are becoming increasingly aware of the environmental impact of their devices and are seeking ways to minimize their energy consumption and carbon footprint. Poly-Si TFT, despite its higher leakage current and reliance on expensive laser annealing techniques, provides a brighter screen brightness and vibrant image quality due to its higher driving current. However, using poly-Si TFT throughout the entire screen would result in high power consumption. Furthermore, producing poly-Si TFTs require the use of excimer laser annealing technology, which is expensive and time-consuming. IGZO TFT, despite its incapable of providing a high driving current due to its small mobility (~10 cm2/(V·s))[28, 29], provides a much smaller power consumption due to its extremely low leakage current. However, using IGZO TFT throughout the entire screen could not provide enough current driving capability to realize high-quality AM displays. Therefore, a more advanced TFT technology is needed to meet these demands for performance and environmental protection. Samsung developed low-temperature polycrystalline oxide (LTPO) technology in 2018 to create a more power-efficient display[30]. This technology utilizes a-IGZO TFTs as switch devices for pixels, while low-temperature poly-Si TFTs act as driver devices for LED pixels to overcome the problem of leakage current in low-temperature poly-Si TFTs[31]. However, implementing LTPO technology necessitates the incorporation of two distinct types of TFTs, namely IGZO TFT and poly-Si TFT, on the same panel. Consequently, the LTPO process is complex and costly. Thus, the current challenge for TFTs is to find a technology that provides low leakage current and high-mobility of TFTs with low fabrication cost to meet the demand for higher-quality AM displays.

    Indium-tin-zinc oxide (ITZO) TFTs are a promising alternative to IGZO TFT, offering a range of advantages such as superior optoelectronic properties, high carrier mobility, and lower consumption. With its larger bandgap[32, 33], ITZO TFT can achieve higher transparency in the visible light range, making it ideal for use in displays and other optoelectronic applications. ITZO TFT features high carrier mobility, facilitated by the direct spatial overlap between the 5 s orbitals of Sn and In[34], which enables easier electron carrier transport. ITZO TFT’s low leakage current makes it an energy-efficient option[35], further reducing costs. Additionally, ITZO TFT’s use of Sn instead of Ga makes it a more cost-effective material because Sn is more readily available. Furthermore, in terms of manufacturing, ITZO TFT can be easily integrated into existing IGZO TFT production lines, which eliminates the need for additional costs[32]. These factors make ITZO TFT a highly commercially viable option, with the potential to replace IGZO TFTs in various applications, especially in high-quality AM displays. Overall, ITZO TFT represents a significant technological advancement in the field of MO TFTs, offering superior performance and cost-effectiveness.

    In the last decade, numerous studies have focused on optimizing and improving ITZO TFT, but a comprehensive review remains lacking. Thus, we have compiled the majority of studies on ITZO TFT from the past decade. With a focus on mobility as the most significant selling point of ITZO TFT, we will provide a thorough overview of the research progress made on this technology in recent years. This paper aims to analyze the advancements made in enhancing the mobility of ITZO TFTs. We will delve into the structure of the TFT and the key parameters utilized to assess its performance, emphasizing the crucial role that high-mobility TFTs play in current technology. We will then present a comprehensive overview of the most recent breakthroughs in ITZO TFT mobility, highlighting the unique innovations featured in each study. Finally, we will conclude with a concise summary and discuss future prospects for the development of ITZO mobility.

    High-mobility ITZO TFTs and performance evaluation

    TFTs typically consist of four main components: a substrate; an active layer; a dielectric layer; and source, drain, and gate components. Weimer's definition[36] classifies TFT devices into two types: coplanar and staggered. Specifically, in a staggered type the gate and source/drain are located on opposite sides of the active layer, while a coplanar type has them located on the same side, as illustrated in Fig. 1. Moreover, TFT structures can also be categorized into top-gate and bottom-gate structures, depending on the location of the gate. As a result, TFTs can be classified into four different structures based on these two classification methods, as shown in Fig. 1. In MO TFTs, the commonly used structures are the bottom-gate staggered type and the top-gate coplanar type.

    (Color online) Schematic diagram of TFT structure classified according to Weimer’s definition and deposition order.

    Figure 1.(Color online) Schematic diagram of TFT structure classified according to Weimer’s definition and deposition order.

    As a type of field-effect transistor, TFTs can be assessed based on different electrical parameters, mainly including subthreshold swing (SS), on/off ratio, threshold voltage (VTH), and mobility, which can be obtained from the device’s transfer curves.

    The SS indicates the sharpness of the subthreshold region in the transfer characteristic curve. It is defined as the absolute value of the change in gate-source voltage (VGS) required to produce a tenfold change in drain-source current (IDS) at a fixed value of drain-source voltage (VDS), and is expressed in units of V/decade. The SS reflects the quality of the channel and the interface between the active layer and dielectric. A lower interface defect density results in a smaller SS and faster device switching speed. The formula to calculate subthreshold swing is as follows[35]:

    SS=(log(IDS)VGS|max)1.

    The on/off ratio is another essential indicator of a TFT’s performance and is normally calculated as the ratio of the maximum IDS (Ion) to the minimum IDS (Ioff) in the transfer characteristic curve[35]. Once the Ion and Ioff are defined, the on/off ratio can be determined.

    The VTH is the voltage value that indicates the transition of a device from the off state to the on state. It refers to the VGS at which the device forms a conductive channel. Various methods[37] can be used to determine the VTH, but the most commonly used method defines it as the gate voltage corresponding to a specific IDS. However, the IDS is affected by VDS and the channel’s width-to-length ratio (W/L). Therefore, the VTH is usually defined using the following formula:

    ITH=IDS/(WL),

    VTH=VGS(ITH=1nA,VDS=0.1V),

    VTH=VGS(ITH=10nA,VDS=5V),

    VTH=VGS(ITH=100nA,VDS=10V),

    where ITH, W, and L are, respectively, the normalized IDS, channel width, and channel length.

    The parameter of mobility characterizes the movement of charge carriers in the channel, and is primarily influenced by the thin film’s quality and the active layer’s interface with the dielectric. It can be used to indirectly assess the active layer’s quality. There are two commonly used methods[37] for extracting mobility. In the linear region (VDSVGSVTH), the linear field-effect mobility (μfe) can be calculated using the linear current equation and the transconductance (gm) of the TFT through:

    IDS=WLμfeCOX[(VGSVTH)VDS12VDS2],

    μfe=IDS/VGSCOXWLVDS=gmCoxWLVDS,

    where Cox is the gate insulator capacitance per unit area. When the device is operated in the saturation region (VDS > VGSVTH), its transfer curve is generally measured at a relatively large VDS. In this case, the saturation region current equation is used to calculate the saturation mobility (μsat) through:

    IDS=12WLμsatCOX(VCSVTH)2,

    μsat=(dIDS/dVGS)212WLCOX.

    TFTs with high mobility typically exhibit a small SS and a large Ion. As depicted in Fig. 2, a traditional two transistors one capacitor (2T1C) pixel driving circuit of AMOLED comprises two TFTs, a capacitor, and an LED. For high refresh rate, high resolution, and high brightness AMOLED displays, the T1 transistor necessitates fast switching speeds (i.e., a small SS), a large Ion for rapid capacitor charging, and a small Ioff to minimize the potential drop of the capacitor within a single frame time. The T2 transistor requires a large Ion to achieve higher OLED excitation brightness. Both small SS and large Ion typically correspond to high mobility. Therefore, ITZO TFTs are well-suited for meeting these requirements.

    Schematic of 2T1C.

    Figure 2.Schematic of 2T1C.

    Advances in high-mobility ITZO TFTs

    As a promising candidate for high-mobility TFTs that could potentially be widely used in the future, ITZO TFT has been extensively studied for performance optimization[3891]. These efforts, as depicted in Fig. 3, can be broadly categorized into five areas: active layer optimization[3862], gate dielectric optimization[6473], electrode optimization[74, 75], interface optimization[7784], and device structure optimization[8591].

    (Color online) Classification of the method to improve ITZO TFT mobility.

    Figure 3.(Color online) Classification of the method to improve ITZO TFT mobility.

    Active layer optimization engineering

    Three main strategies are normally employed to optimize the active layer of ITZO TFTs: optimizing the film preparation process[3849], doping the film[5055], and post-treating the film[5662]. A summary of active layer optimization is shown in Table 1.

    Table Infomation Is Not Enable

    Optimization of deposition technology

    ITZO film is typically prepared using sputtering deposition[3843]. Researchers have focused on improving the quality of sputtered ITZO films to enhance their mobility for years. In 2013, Jang et al.[38] conducted an experiment that showed the close relationship between the quality of sputtered ITZO films and the oxygen (O2) ratio in the gas used. Although there were slight differences in the proportions of the three elements in the films sputtered at different O2 ratios, these differences had a significant impact. The content of In element showed a trend of first decreasing and then increasing with the increase of O2 ratio. When the proportion of In element was the lowest, the performance of the device obtained by sputtering was the best, with a mobility of 37.2 cm2/(V·s) and an SS of 0.93 V/dec. In 2014, Kim et al.[39] co-sputtered ITZO TFTs using ITO and ZTO targets to further explore the effect of In element on device performance under large variations in content. This experiment showed that increasing In element content improved the device mobility. Furthermore, increasing In element content brought a negative VTH shift. Appropriate In element doping can improve the stability and mobility of the device by promoting the formation of Sn2+–O2‒ bonds in ITZO films, compensating for the oxygen vacancies in ITZO films. The final prepared ITZO TFT had a mobility larger than 30 cm2/(V·s). In 2018, Park et al.[40] compared ITZO TFT devices sputtered at different O2 ratios and found that an increase in O2 ratio significantly inhibited the content of oxygen vacancies in the film. Oxygen vacancies, as common carrier donors in MO films, can make the device easier to turn on and result in a larger negative VTH shift when there are too many oxygen vacancies. In 2021, Wu et al.[41] explored the relationship between target quality and device performance. The experimental results showed that using targets with higher density and better crystallinity can achieve high mobility while maintaining good stability for ITZO TFTs. Serious preferential sputtering occurs when sputtering low-density targets, which makes the particles stack on the substrate in a more disorderly manner. By using high-density targets and appropriate power, the final prepared ITZO TFTs had a mobility of up to 36.1 cm2/(V·s) and a VTH shift of only ‒0.55 V under negative bias stress (NBS) of ‒20 V for 3600 s (Fig. 4).

    (Color online) (a) Transfer characteristics at VDS = 10.1 V, (b) stress-time dependent variation of ITZO TFTs (fabricated by ITZO-1 and ITZO-2 at different powers (60, 80, and 100 W)) at NBS (‒20 V, 3600 s). (c) SEM pattern of ITZO-1. (d) SEM patterns of ITZO-2. (e) Table of film properties and deposition parameters. (f) Table of physical parameters of the target[41]. (a)–(f), © 2021 IEEE. Reprinted, with permission, from Ref. [41].

    Figure 4.(Color online) (a) Transfer characteristics at VDS = 10.1 V, (b) stress-time dependent variation of ITZO TFTs (fabricated by ITZO-1 and ITZO-2 at different powers (60, 80, and 100 W)) at NBS (‒20 V, 3600 s). (c) SEM pattern of ITZO-1. (d) SEM patterns of ITZO-2. (e) Table of film properties and deposition parameters. (f) Table of physical parameters of the target[41]. (a)–(f), © 2021 IEEE. Reprinted, with permission, from Ref. [41].

    Besides the sputtering deposition methods, other methods[4449] have also been explored for optimizing film quality. In 2009, Lee et al.[44] used inkjet printing to prepare ITZO TFT on a glass substrate, with a mobility of 30 cm2/(V·s) and a VTH close to 2 V. However, its high annealing temperature (600 °C) and poor SS require further optimization. In 2011, Kim et al.[45] used the same precursor solution as inkjet printing to prepare ITZO TFT by spin-coating. Its mobility was 4.36 cm2/(V·s) and the film annealing temperature was still high at 600 °C. Both methods[44, 45] require high VDS > 30 V for better performance. In 2019, Bukke et al.[46] found that purifying the precursor solution could improve the performance of ITZO devices prepared by spin-coating, achieving a relatively high mobility of 9.50 cm2/(V·s), near-zero VTH (0.51 V), small SS (0.087 V/dec), high stability, and a low preparation temperature (300 °C). In 2019, Sheng et al.[47] employed atomic layer deposition (ALD) to fabricate ITZO films. They deposited ZnO, SnO, and InO using multiple deposition subcycles. Among the different combinations tested, the ITZO TFTs prepared with one In-O cycle, one Zn-O cycle, and one Sn-O cycle demonstrated the highest performance. These devices exhibited a mobility of 27.8 cm2/(V·s) and a VTH of ‒1.2 V. In the same year, Beak et al.[48] used ALD to prepare ITZO TFT and found that the device reached optimal performance under the condition of In/Zn/Sn = 10 : 70 : 20 and annealed at 400 °C, achieving a mobility of 22 cm2/(V·s), an SS of 0.15 V/dec, and a VTH of 0.8 V. In 2020, Liu et al.[49] successfully prepared high-quality ITZO TFTs by ultrasonic spray pyrolysis deposition, achieving a high mobility of 43.84 cm2/(V·s) and an SS of 0.0974 V/dec, exceeding the performance of the traditional spin-coating method and even the widely used sputtering method (Fig. 5).

    (Color online) (a) XRD patterns of USPD- and sputter-deposited ITZO films. (b) PL spectra of USPD- and sputter-deposited ITZO films. (c) Hysteretic IDS-VGS characteristics of TFT-A (USPD-deposited) and TFT-B (sputter-deposited). (d) SS versus stress time (NBIS and PBIS) characteristics of TFT-A and TFT-B[49]. (a)–(d), © 2020 IEEE. Reprinted, with permission, from Ref. [49].

    Figure 5.(Color online) (a) XRD patterns of USPD- and sputter-deposited ITZO films. (b) PL spectra of USPD- and sputter-deposited ITZO films. (c) Hysteretic IDS-VGS characteristics of TFT-A (USPD-deposited) and TFT-B (sputter-deposited). (d) SS versus stress time (NBIS and PBIS) characteristics of TFT-A and TFT-B[49]. (a)–(d), © 2020 IEEE. Reprinted, with permission, from Ref. [49].

    Doping

    On traditional silicon, doping is used to regulate its conductivity[5055]. However, in MOs, doping plays a different role in balancing mobility and stability. In 2018, Li et al.[50] doped lithium (Li) into ITZO thin films and discovered that Li could regulate oxygen vacancies. This reduced scattering centers and increased mobility, resulting in the mobility of 39.1 cm2/(V·s). However, even after the process was optimized[51], a negative VTH shift remained. In 2019, Zhang et al.[52] doped Yttrium (Y) into the active layer of ITZO TFTs using a solution process. Stability tests showed that the stability of ITZO:Y TFTs improved with an increase in the concentration of doped Y, while the mobility decreased. This happened because Y doping suppresses defects, resulting in better SS, but at the cost of reduced mobility due to the consumption of oxygen vacancies. In 2022, Zhang et al.[53] doped praseodymium (Pr) into ITZO TFTs using sputtering, significantly improving their stability while sacrificing only a small amount of mobility. In 2017, Jia et al.[54] introduced nitrogen (N) during the sputtering of ITZO thin films, resulting in the formation of InN nanocrystalline phases, which increased device mobility. Li et al.[55] also found crystallization in ITZO TFTs by introducing nitrogen during their preparation. However, the thick film caused scattering effects from increased carriers, while the presence of oxygen vacancy defects suppressed SS and mobility.

    Post-treatment

    After the film preparation, post treatments[5662] are often necessary to repair the thin film and activate the rearrangement of atoms inside it, achieving a more ordered state. Annealing[5658], as the most commonly used post-treatment, requires optimization in various aspects, mainly including temperature, time, and atmosphere. Fhu et al.[56] investigated the relationship between the ITZO TFT prepared by sputtering and the annealing temperature. They observed that as the annealing temperature increases, the degree of repair of internal defects in the thin film gradually increases, which in turn enhances the device mobility. They also found that increasing the temperature inhibits the defect density inside the thin film, leading to a significant increase in the characteristic trapping time of carriers, thereby establishing a proportionality between device mobility and annealing temperature. Furthermore, Zhong et al.[57] provided partial evidence supporting this conclusion through X-ray photoelectron spectroscopy (XPS) and photoluminescence (PL) characterization techniques. It has also been observed in experiments that excessively high temperatures can lead to the generation of more defects due to the presence of weak bonds inside the thin film. These bonds can easily be broken at high temperatures, causing the formation of new defects. Ultimately, the optimal annealing temperature for ITZO TFT was determined to be 300 °C, which is also the temperature that is commonly used in most ITZO TFT reports. Devices fabricated under these conditions exhibit a high mobility of 27.4 cm2/(V·s), a low VTH of 0.64 V, and a steep SS of 0.23 V/dec.

    Rapid thermal annealing (RTA), as a relatively new post-treatment technology, has been welcomed because it can reach high temperatures in a short time and control the gas atmosphere more accurately. In 2020, Maeng et al.[58] conducted a study on the impact of O2 pressure during the post-treatment of ITZO TFT by RTA. Their research revealed that the amount of oxygen vacancies is directly proportional to the O2 pressure, and as a result the device’s mobility decreases.

    In 2020, Park et al.[59] investigated the relationship between the device performance and high annealing temperature. Their study revealed that when the ITZO TFT was annealed at a temperature of 700 °C, clear crystallization phenomena were observed in the transmission electron microscope (TEM) image. TFTs prepared under this condition showed high mobility of 33.6 cm2/(V·s) and a VTH value very close to 0 V (0.83 V). Although TFTs are typically prepared at low temperatures, Park et al.’s research provided initial insights into the mobility and stability of ITZO TFTs after crystallization. Wang et al.[60] used a different approach called metal-induced crystallization (MIC) to crystallize ITZO. They coated a 15 nm layer of aluminum (Al) metal on the back-channel surface of the ITZO TFT and annealed it below 400 °C. TEM images showed clear crystallization phenomena. This occurred because Al can easily oxidize and generate aluminum oxide (Al2O3) with the O2 inside the thin film, releasing electrons that break weak internal bonds of the thin film, which then rearrange at higher temperatures to achieve crystallization. The ITZO TFT prepared at 400 °C had a high mobility of 53.2 cm2/(V·s). Similarly, Kim et al.[61] utilized tantalum (Ta) as an inducing element for MIC. As a potent reducing agent, Ta has a comparable effect as Al in breaking weak bonds inside the thin film and rearranging them at high temperatures. Different element ratios tend to produce different types and quantities of crystal lattice structures after rearrangement. Therefore, by optimizing the element ratio of the ITZO thin film, a single orientation of crystallization can be achieved. It was found that the best electrical performance of the device was achieved when the In : Zn : Sn ratio was 22 : 55 : 23, resulting in a mobility of over 80 cm2/(V·s) and very high stability (Fig. 6).

    (Color online) (a) InO0.5–ZnO–SnO2 phase diagram. (b) Schematic of IZTO TFT after RIE etching. Box plots of (c) μfe and (d) VTH for devices with different Zn fractions[61]. (a)–(d), Ref. [61], John Wiley & Sons. [© 2023 Wiley-VCH GmbH].

    Figure 6.(Color online) (a) InO0.5–ZnO–SnO2 phase diagram. (b) Schematic of IZTO TFT after RIE etching. Box plots of (c) μfe and (d) VTH for devices with different Zn fractions[61]. (a)–(d), Ref. [61], John Wiley & Sons. [© 2023 Wiley-VCH GmbH].

    Gate dielectric engineering

    Gate dielectric, as a critical component that strongly affects the gate control of the channel, has been extensively studied for its impact on the performance of the channel[63], as well as its compatibility with ITZO[6473]. The high-quality gate dielectric is typically characterized by a higher degree of density and a smoother film surface. Thinning down the gate insulator layer can enhance the gate-control ability over the channel; however, if the layer is too thin, it can result in large leakage currents. Therefore, high-k materials are commonly employed as gate dielectrics. In this section, we will present and discuss the research related to gate insulation layer engineering in ITZO TFTs, as summarized in Table 2.

    Table Infomation Is Not Enable

    Al2O3 is commonly used as high-k dielectric in ITZO TFTs[65, 66]. In 2013, Jiang et al.[65] compared silicon nitride (Si3N4) and Si3N4/Al2O3 as gate dielectrics for ITZO TFTs. Although the two materials have similar relative dielectric constants, Al2O3 has a denser and smoother surface due to the fabrication process, resulting in higher device mobility and stability. A smoother and denser surface can introduce fewer defects in the channel, reducing the probability of carrier scattering and thus improving device mobility. In 2016, Raja et al.[66] found that soaking the Al2O3 thin film in a hydrogen peroxide solution could effectively reduce the defects inside the film, resulting in a certain increase in both mobility and SS.

    Zirconium oxide (ZrO2) has been extensively investigated as an insulating layer in ITZO TFTs[6872]. This is due to its high relative dielectric constant of 25, which surpasses that of Al2O3[67]. In 2018, Ruan et al.[68] conducted a study on ITZO TFTs with three different insulating layers: hafnium oxide (HfO2), ZrO2, and Al2O3. The authors showed that ITZO TFTs with ZrO2 gate insulators exhibited a steep SS of 0.126 V/dec and a high mobility of 40.7 cm2/(V·s), while HfO2, which has a similar dielectric constant, showed a mobility of 16.1 cm2/(V·s). The ZrO2 thin film used in the process had more oxygen vacancies, which can capture O2 from the active layer and increase the oxygen vacancy concentration in the channel after the film is fabricated into a TFT. This leads to a slightly degraded SS in ZrO2-ITZO TFTs compared to HfO2-ITZO TFTs. However, this degradation is acceptable compared to the improvement in mobility. In 2018, Bukke et al.[69] found that purifying the precursor solution of ZrO2 and spin-coating it could improve the quality of the gate insulator film in solution-processed ITZO TFTs because the ZrO2 thin film prepared by spin-coating the purified solution has a smoother surface, which reduces the defects inside the channel and ultimately leads to a significant improvement in mobility. In the same year, Bukke et al.[70] also introduced hafnium alloy into ZrO2 thin films, which also led to a smoother surface and improved mobility. In 2019, Kim et al.[71] compared ITZO TFTs fabricated with ZrO2 and zirconium silicate (ZrSiOx) as gate-insulating layers. They found that although ZrO2 has a high dielectric constant, its thin film surface is relatively rough, leading to a large leakage current due to crystallization. In ZrSiOx, the introduction of Si can effectively inhibit the crystallization of ZrO2, resulting in a sufficiently smooth thin film surface. Therefore, ITZO TFTs with ZrSiOx as the insulating layer had the highest mobility, the smallest SS, and the highest stability among the three materials. Choi et al.[72] adopted another approach to address the high surface roughness of ZrO2 thin films. Although silicon oxide (SiO2) has a lower dielectric constant, its smooth thin film surface can help to form better-quality conductive channels. Therefore, a series-connected gate dielectric layer consisting of SiO2 and ZrO2 was used to obtain a surface-smooth and high-dielectric-constant gate insulator. Ultimately, they found that depositing 8 nm of SiO2 on ZrO2 resulted in the highest mobility of 27.7 cm2/(V·s) and the best stability (Fig. 7). In 2022, Zhong et al.[73] used a similar method to spin-coat organic compound triethoxysilane-based self-assembled monolayers with eight alkyl on Al2O3, which significantly suppressed the surface roughness of the film, reduced the oxygen vacancies on the film surface, and ultimately improved the mobility and stability of the device to a certain extent.

    (Color online) (a) Representative transfer characteristics depending on the thickness combination of ZrO2/SiO2 films. (b) VTH shift during PBTS test. (c) Parameter shift of each TFT after 3600 s of PBTS test[72]. (a)–(c), used with permission of Royal Society of Chemistry, reprinted from Ref. [72] , 2020.

    Figure 7.(Color online) (a) Representative transfer characteristics depending on the thickness combination of ZrO2/SiO2 films. (b) VTH shift during PBTS test. (c) Parameter shift of each TFT after 3600 s of PBTS test[72]. (a)–(c), used with permission of Royal Society of Chemistry, reprinted from Ref. [72] , 2020.

    Electrode optimization engineering

    The contact between the source and drain electrodes and the active layer, serving as the emission and collection ports of channel electrons, is a critical aspect of this debate that is worth exploring. However, there has been little research conducted on this aspect for ITZO TFT electrodes[74, 75]. In 2015, Park et al.[74] conducted a comparison of nickel (Ni), indium tin oxide (ITO), and Al electrodes’ compatibility with ITZO TFTs. The authors showed that Ni has the smallest contact resistance with ITZO due to the closest work function match, resulting in the best Ion performance (Figs. 8(a) and 8(b)). Conversely, the use of Al electrodes resulted in lower open-state current and more severe negative VTH shift. In 2020, the same research group[75] carried out a more detailed investigation into this issue. They discovered that O2 from the thin film diffuses into the electrode, resulting in the formation of AlxOy and nickel oxide (NiOx) on the contact surface between the electrode and the active layer when using Al as the electrode. Compared to NiOx, AlxOy has a higher oxygen vacancy concentration, which quickly diffuses into the channel after annealing, resulting in a surge in channel carrier concentration and leading to negative VTH shift (Figs. 8(c) and 8(d)).

    (Color online) (a) Transfer characteristics (at VDS = 1 V) of ITZO TFTs with different S/D contacts; (b) schematic band diagram for ITZO TFT with Al, ITO, and Ni electrodes[74]. (a) and (b) reprinted from Ref. [74], Copyright (2015), with permission from Elsevier. (c) Schematics of the diffusion of oxygen vacancies in the ITZO layer from Al S/D electrodes[75]. (d) Schematics of the diffusion of oxygen vacancies in the ITZO layer from Ni S/D electrodes[75]. (c) and (d) Reprinted from Ref. [75], Copyright (2020), with permission from Elsevier.

    Figure 8.(Color online) (a) Transfer characteristics (at VDS = 1 V) of ITZO TFTs with different S/D contacts; (b) schematic band diagram for ITZO TFT with Al, ITO, and Ni electrodes[74]. (a) and (b) reprinted from Ref. [74], Copyright (2015), with permission from Elsevier. (c) Schematics of the diffusion of oxygen vacancies in the ITZO layer from Al S/D electrodes[75]. (d) Schematics of the diffusion of oxygen vacancies in the ITZO layer from Ni S/D electrodes[75]. (c) and (d) Reprinted from Ref. [75], Copyright (2020), with permission from Elsevier.

    Interface engineering

    High-mobility MO semiconductors tend to have deeper conduction band bottom energy levels[32]. This makes them more vulnerable to impurities and moisture at the back channel, which can reduce stability under continuous stress. Additionally, hanging bonds at the back channel can easily be trapped by electron traps formed by moisture and other substances in the air, resulting in poor initial device performance. The most common approach to improve the back channel is to add a passivation layer to isolate water and O2 and eliminate hanging bonds[7784]. In this section, we will showcase the advancements in optimizing the back-channel interface of ITZO TFTs, highlighting the outcomes of these endeavors (Table 3).

    Table Infomation Is Not Enable

    In recent years, numerous studies[7779] have focused on passivation layers to improve the stability of high-mobility MO semiconductors, which are often prone to the effects of impurities and moisture at the back channel. Among these studies, self-assembled monolayers (SAMs) have emerged as a promising option due to their chemical and physical resistance, and ability to withstand thermal annealing and plasma treatment[76]. However, the most suitable type of SAMs for passivation layers in ITZO TFTs remains an area of ongoing research. In 2018, Zhong et al.[77] investigated the feasibility of using three different alkyl chain length triethoxysilane-based SAMs as passivation layers for ITZO TFTs. They found that hydrophobic SAMs spin-coated at the back channel can effectively block the adhesion of moisture and other substances, leading to improved stability of the device. In 2020, they used the method of gas-phase deposition to prepare n-octyltriethoxysilane SAMs (OTES) as a passivation layer and obtained similar results[78] (Fig. 9). In 2021, Chen et al.[79] prepared octadecylamine as the passivation layer on the back-gate channel of ITZO TFT using evaporation and explored the relationship between evaporation time and the device’s electrical properties and stability. They found that longer evaporation times improved hydrophobicity, mobility, and stability, but also caused a negative VTH shift. It should be noted that the SAMs are usually organic, which is incompatible with the industry production lines of AM displays.

    (Color online) (a) Transfer characteristics of untreated and OTES-treated ITZO TFTs on PI substrates. (b) Plot of μfe as a function of gate bias. (c) Variations in threshold voltage shift for untreated and OTES-treated ITZO TFTs, as a function of stress time under separate gate bias voltages of 10 and −10 V. XPS spectra of O 1s peaks of (d) untreated and (e) OTES-treated ITZO films[78]. (a)–(e), © 2020 IEEE. Reprinted, with permission, from Ref. [78].

    Figure 9.(Color online) (a) Transfer characteristics of untreated and OTES-treated ITZO TFTs on PI substrates. (b) Plot of μfe as a function of gate bias. (c) Variations in threshold voltage shift for untreated and OTES-treated ITZO TFTs, as a function of stress time under separate gate bias voltages of 10 and −10 V. XPS spectra of O 1s peaks of (d) untreated and (e) OTES-treated ITZO films[78]. (a)–(e), © 2020 IEEE. Reprinted, with permission, from Ref. [78].

    Apart from SAMs, many inorganic materials can also be utilized as passivation layers to enhance the performance of ITZO TFTs[8082]. In 2016, Bukke et al.[80] prepared Yttrium oxide (Y2O3) as a passivation layer by spin-coating it onto the back-gate channel of ITZO TFTs. The authors found that Y2O3 not only served as a passivation layer but also diffused Y elements partially into the ITZO thin film, playing a doping role. XPS characterization results indicated that Y2O3 passivation reduced the oxygen vacancy of the device, increased the M–O–M bond content, and suppressed oxygen vacancy defects by doping Y elements, thereby improving the mobility and SS of the device. In 2021, Zhong et al.[81] investigated the use of Al2O3 and scandium oxide (Sc2O3) as passivation layers for ITZO TFTs and compared their performance. The results showed that Sc2O3 had a greater ability to isolate water vapor and air than Al2O3 and had fewer oxygen vacancies at the back-gate channel interface (Fig. 10). Thus, ITZO passivated by Sc2O3 had higher mobility and stability. In 2022, Shi et al.[82] used GaO as a passivation layer for ITZO TFTs and developed a tetramethyl ammonium hydroxide (TMAH) developer that could simultaneously etch ITZO and GaO. The TMAH developer's development reduced the preparation process's complexity by reducing the two mask patterns to one. The mobility and stability of the device were also significantly enhanced due to the coverage of the GaO passivation layer.

    (Color online) O 1s spectra of the back channel of the ITZO TFTs (a) without a PVL, (b) with an Al2O3 passivation layer, and (c) with a Sc2O3 passivation layer. (d) Transfer characteristics of the ITZO TFTs with no passivation layer, Al2O3 passivation layer and Sc2O3 passivation layer. (e) Plot of µfe as a function of gate bias[81]. (a) –(e), © 2021 IEEE. Reprinted, with permission, from Ref. [81].

    Figure 10.(Color online) O 1s spectra of the back channel of the ITZO TFTs (a) without a PVL, (b) with an Al2O3 passivation layer, and (c) with a Sc2O3 passivation layer. (d) Transfer characteristics of the ITZO TFTs with no passivation layer, Al2O3 passivation layer and Sc2O3 passivation layer. (e) Plot of µfe as a function of gate bias[81]. (a) –(e), © 2021 IEEE. Reprinted, with permission, from Ref. [81].

    In 2021, Shiah et al.[83] found that impurities on the surface of the back channel also need to be removed before adding a passivation layer. They found that C-related impurities, originating from photoresist and remaining at the back channel during lithography, are the main cause of NBS instability in these devices. The study suggests that these impurities can be eliminated by additional UV ozone treatment (Fig. 11).

    (Color online) (a) Carbon 1s HAX-PES spectra of as-deposited and post-treated ITZO films. NBS stability of ITZO TFTs (b) without CO exposure, (c) with CO2 exposure, and (d) with CO exposure. (e) Threshold voltage shift of TFTs with different treatment under NBS. (f) NBS stability and (g) PBS stability of UV ozone treated ITZO TFT[83]. (a)–(g) , © 2021 IEEE. Reprinted, with permission, from Ref. [83].

    Figure 11.(Color online) (a) Carbon 1s HAX-PES spectra of as-deposited and post-treated ITZO films. NBS stability of ITZO TFTs (b) without CO exposure, (c) with CO2 exposure, and (d) with CO exposure. (e) Threshold voltage shift of TFTs with different treatment under NBS. (f) NBS stability and (g) PBS stability of UV ozone treated ITZO TFT[83]. (a)–(g) , © 2021 IEEE. Reprinted, with permission, from Ref. [83].

    Device structure optimization

    Another major research focus is to enhance device performance by modifying the device structure. There are diverse solutions in this field, which can generally be divided into two categories: the first is to make structural adjustments only on the simple ITZO TFT[8588], and the second is to introduce other materials as auxiliaries[8991].

    When reducing the size of device features, device performance, such as mobility, can often deteriorate. Structural optimization can help to improve this. In 2017, Xia et al.[85] developed the elevated-metal metal-oxide (EMMO) structure for ITZO TFTs. This structure cleverly utilizes the difference in permeability between SiO2 and MO. After depositing a layer of SiO2 on IGZO and defining the source-drain metal, O2 enters the ITZO through the permeable SiO2 to repair defects, while the non-permeable metal covering ITZO exhibits very low resistivity and becomes conductive (Fig. 12(d)). In contrast to the original etch stop (ES) structure, defining the L through the distance between the electrodes can not only retain the ES layer to reduce the degradation of device performance but also obtain a smaller L, thereby reducing the device area (Figs. 12(a)−12(c)). However, shortening L can cause hydrogen in the passivation layers, such as alumina, to diffuse into the channel after annealing. When the L is too short, the gate loses its ability to control the channel due to the increased conductivity of the active layer. In 2021, Kim et al.[86] addressed this issue by developing a self-aligned ITZO TFT with a trench structure. Due to the roughness inside the trench, especially the sidewalls, the interior of the groove still maintains a high resistivity. At higher temperatures, the device can still maintain its switching performance. The mobility of the device can reach nearly 100 cm2/(V·s) at 270 °C annealing while still maintaining high stability (Figs. 12(e) and 12(f)).

    (Color online) The cross-sectional schematics of (a) an EMMO and (b) an ES TFT and the corresponding layouts of a 500-ppi AMLCD sub-pixel based on (c) an EMMO and an ES TFT with a W/L of 2.5 and a design-rule of 2 µm. (d) The dependence of the resistivity values of metal- and oxide-covered ITZO on thermal treatment time. Shown in the inset are the transfer characteristics of EMMO ITZO TFTs with and without going through a thermal annealing process[85]. (a)–(d), © 2017 IEEE. Reprinted, with permission, from Ref. [85]. (e) Schematic diagrams of planar SA TFT (left) and trench SA TFT (right). (f) Transfer curves of planar and trench TFTs before annealing (left-hand panel) and after annealing at 270 °C (right-hand panel)[86]. (e)–(f), © 2021 IEEE. Reprinted, with permission, from Ref. [86]. (g) ITZO TFTs with different channel structures: device A contains an oxygen-uncompensated channel layer (UCL) and device B contains a bilayer channel, which is an oxygen-compensated channel layer (CCL) and an oxygen-uncompensated channel layer (UCL). (h) Output characteristics of device A and device B[87]. (g)–(h) , reprinted with permission from Ref. [87]. Copyright 2022, American Chemical Society.

    Figure 12.(Color online) The cross-sectional schematics of (a) an EMMO and (b) an ES TFT and the corresponding layouts of a 500-ppi AMLCD sub-pixel based on (c) an EMMO and an ES TFT with a W/L of 2.5 and a design-rule of 2 µm. (d) The dependence of the resistivity values of metal- and oxide-covered ITZO on thermal treatment time. Shown in the inset are the transfer characteristics of EMMO ITZO TFTs with and without going through a thermal annealing process[85]. (a)–(d), © 2017 IEEE. Reprinted, with permission, from Ref. [85]. (e) Schematic diagrams of planar SA TFT (left) and trench SA TFT (right). (f) Transfer curves of planar and trench TFTs before annealing (left-hand panel) and after annealing at 270 °C (right-hand panel)[86]. (e)–(f), © 2021 IEEE. Reprinted, with permission, from Ref. [86]. (g) ITZO TFTs with different channel structures: device A contains an oxygen-uncompensated channel layer (UCL) and device B contains a bilayer channel, which is an oxygen-compensated channel layer (CCL) and an oxygen-uncompensated channel layer (UCL). (h) Output characteristics of device A and device B[87]. (g)–(h) , reprinted with permission from Ref. [87]. Copyright 2022, American Chemical Society.

    As AM displays continue to advance with high resolution, the pixels shrink in size, necessitating the scaling down of MO TFTs. Therefore, studying the scaling behavior of ITZO TFTs is of great importance. This analysis would provide valuable insights into the performance and limitations of these devices as they are miniaturized. Factors like L, contact resistance, and gate insulator thickness can have a significant impact on the device characteristics at smaller dimensions. Understanding the scaling behavior is crucial for optimizing device performance and addressing potential challenges associated with miniaturization. However, there are currently limited reports available on the scaling behaviors of ITZO TFTs, which highlights the need for further exploration in this direction.

    Mobility of ITZO TFT can be also improved by adjusting the device structure[87, 88]. Lee et al.[87] achieved significant improvements in mobility and stability by covering a 1 nm oxygen-rich ITZO film on top of the ITZO channel in a similar way to the passivation layer (Figs. 12(g) and 12(h)). The XPS characterization results showed that the oxygen vacancy content of the oxygen-rich ITZO layer was significantly lower than that of the low-oxygen layer, and the proportion of O–M–O bonds increased significantly. Thus, the oxygen-rich layer was less sensitive to air and water vapor and could act as a passivation layer. Additionally, oxygen from the oxygen-rich layer entered the low-oxygen layer to repair defects, further improving the film's quality. The performance improvement from this structure was ultimately reflected in a significant increase in mobility and stability.

    By incorporating other materials, the performance of ITZO TFT can be enhanced[8991]. In 2017, Nguyen et al.[89] introduced a very thin layer of ITO into the channel of ITZO TFT, resulting in a significant improvement in the device’s mobility. However, if the ITO layer was too thin, then an island-like structure that was not fully formed could result in too many heterojunctions in the channel, which increases the likelihood of carrier scattering and ultimately leads to a decrease in mobility. When the inserted ITO layer reached a thickness of 5 nm, it provided more carriers, resulting in a significant increase in mobility (Figs. 13(a)−13(c)). Further increasing the thickness of the ITO layer would produce too many carriers, decreasing the gate-control capability and causing the device to directly conduct. Ultimately, after inserting a 5 nm ITO layer, the double-layer ITZO TFT reached a high mobility of 95 cm2/(V·s) while still maintaining excellent stability.

    (Color online) (a) Device structure of the bilayer ITO/ITZO TFT device. (b) Transfer characteristics of TFT devices with different ITO thicknesses. (c) Corresponding output characteristics of ITO/ITZO TFT devices[89]. (a)–(c), Reprinted from Ref. [89], Copyright (2016), with permission from Elsevier. (d) Contour of current density for off state. (e) Transfer characteristics of corrugated heterostructure ITZO (5.4 nm)/IGZO (20 nm) heterostructure, ITZO (10 nm)–IGZO (20 nm) heterostructure. (f) Electron concentration as a function of the gate voltage sweep (−15 to 15 V) in the indicated thick- (region #1) and thin-ITZO/IGZO heterointerface (region #2)[90]. (d)–(f) Ref. [90], John Wiley & Sons. [© 2018 Wiley-VCH GmbH].

    Figure 13.(Color online) (a) Device structure of the bilayer ITO/ITZO TFT device. (b) Transfer characteristics of TFT devices with different ITO thicknesses. (c) Corresponding output characteristics of ITO/ITZO TFT devices[89]. (a)–(c), Reprinted from Ref. [89], Copyright (2016), with permission from Elsevier. (d) Contour of current density for off state. (e) Transfer characteristics of corrugated heterostructure ITZO (5.4 nm)/IGZO (20 nm) heterostructure, ITZO (10 nm)–IGZO (20 nm) heterostructure. (f) Electron concentration as a function of the gate voltage sweep (−15 to 15 V) in the indicated thick- (region #1) and thin-ITZO/IGZO heterointerface (region #2)[90]. (d)–(f) Ref. [90], John Wiley & Sons. [© 2018 Wiley-VCH GmbH].

    In 2018, Lee et al.[90] reported on an IGZO/ITZO TFT with a corrugated heterojunction channel structure. Due to the heterojunction’s diode-like characteristics, when under negative gate voltage, the carriers become trapped at the heterojunction interface, similar to a diode’s reverse bias. Conversely, when under positive gate voltage, the heterojunction barrier is flattened, releasing a large number of electrons into the channel, greatly enhancing channel conductivity. However, in a planar structure heterojunction, the heterojunction is horizontally continuous, and the device’s leakage current can easily increase due to the heterojunction continuously providing carriers to the source electrode when turned off. The corrugated structure of the heterojunction interface breaks the horizontal continuity of the heterojunction, so it does not continuously provide carriers to the source electrode, greatly reducing the off-state current of the device (Figs. 13(d)−13(f)).

    Conclusion

    Over the past decade, significant progress has been made in improving the performance of ITZO TFT through process optimization. This article reviews the various methods that have been used to prepare ITZO films and optimize the active layer, with a focus on sputtering. We also explore doping methods, post-treatment techniques, and high-k dielectrics. Ni has been identified as a suitable electrode material, and the role of passivation layers in optimizing back-channel surfaces is emphasized. Structural optimization has also been discussed from two perspectives: solo ITZO structure and introducing other materials. Despite progress in improving mobility, stability remains a challenge. There is a trade-off between mobility and stability, which must be addressed after achieving high mobility levels. Nonetheless, several methods that can improve mobility while maintaining high stability have been identified. The next step is to continue improving mobility while ensuring device stability within an acceptable range. Although many problems remain, ITZO TFT devices have surpassed traditional IGZO TFTs in terms of performance. The development in ITZO TFT-related technologies will undoubtedly contribute to future high-quality display panels.

    References

    [1] T Hirao, M Furuta, H Furuta et al. Novel top-gate zinc oxide thin-film transistors (ZnO TFTs) for AMLCDs. Journal of the Society for Information Display, 15, 17(2007).

    [2] M Stewart, R S Howell, L Pires et al. Polysilicon TFT technology for active matrix OLED displays. IEEE Trans Electron Devices, 48, 845(2001).

    [3] C D Sheraw, L Zhou, J R Huang et al. Organic thin-film transistor-driven polymer-dispersed liquid crystal displays on flexible polymeric substrates. Appl Phys Lett, 80, 1088(2002).

    [4] J Y Kwon, K S Son, J S Jung et al. Bottom-gate gallium indium zinc oxide thin-film transistor array for high-resolution AMOLED display. IEEE Electron Device Lett, 29, 1309(2008).

    [5] A Nathan, A Kumar, K Sakariya et al. Amorphous silicon thin film transistor circuit integration for organic LED displays on glass and plastic. IEEE J Solid State Circuits, 39, 1477(2004).

    [6] P K Weimer. The TFT A new thin-film transistor. Proc IRE, 50, 1462(1962).

    [7] S W Luan, G W Neudeck. An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors. J Appl Phys, 72, 766(1992).

    [8] K Sera, F Okumura, H Uchida et al. High-performance TFTs fabricated by XeCl excimer laser annealing of hydrogenated amorphous-silicon film. IEEE Trans Electron Devices, 36, 2868(1989).

    [9] H Kuriyama, S Kiyama, S Noguchi et al. Enlargement of poly-Si film grain size by excimer laser annealing and its application to high-performance poly-Si thin film transistor. Jpn J Appl Phys, 30, 3700(1991).

    [10] S D Brotherton. Polycrystalline silicon thin film transistors. Semicond Sci Technol, 10, 721(1995).

    [11] Z G Meng, M X Wang, M Wong. High performance low temperature metal-induced unilaterally crystallized polycrystalline silicon thin film transistors for system-on-panel applications. IEEE Trans Electron Devices, 47, 404(2000).

    [12] X F Zhao, D Z Wen, C C Zhuang et al. Fabrication and characteristics of magnetic field sensors based on nano-polysilicon thin-film transistors. J Semicond, 34, 036001(2013).

    [13] W S Cai, H Y Li, M C Li et al. Performance enhancement of solution-processed InZnO thin-film transistors by Al doping and surface passivation. J Semicond, 43, 034102(2022).

    [14] Y Y Liang, J Kyungsoo, S Velumani et al. Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor. J Semicond, 36, 024007(2015).

    [15] X M Zhu, H Z Wu, S J Wang et al. Optical and electrical properties of N-doped ZnO and fabrication of thin-film transistors. J Semicond, 30, 033001(2009).

    [16] Y Zhu, Y L He, S S Jiang et al. Indium–gallium–zinc–oxide thin-film transistors: Materials, devices, and applications. J Semicond, 42, 031101(2021).

    [17] P Mittal, Y S Negi, R K Singh. Impact of source and drain contact thickness on the performance of organic thin film transistors. J Semicond, 35, 124002(2014).

    [18] Z F Li, X Y Luo. ADO-phosphonic acid self-assembled monolayer modified dielectrics for organic thin film transistors. J Semicond, 35, 104004(2014).

    [19] C L Lin, M H Cheng, C D Tu et al. Highly reliable integrated gate driver circuit for large TFT-LCD applications. IEEE Electron Device Lett, 33, 679(2012).

    [20] C W Liao, C D He, T Chen et al. Design of integrated amorphous-silicon thin-film transistor gate driver. J Disp Technol, 9, 7(2013).

    [21] C L Lin, C D Tu, M C Chuang et al. Design of bidirectional and highly stable integrated hydrogenated amorphous silicon gate driver circuits. J Disp Technol, 7, 10(2011).

    [22] T Tanaka, H Asuma, K Ogawa et al. An LCD addressed by a-Si: H TFTs with peripheral poly-Si TFT circuits. Proceedings of IEEE International Electron Devices Meeting. Washington, DC, USA. IEEE, 389(2002).

    [23] K Nomura, H Ohta, A Takagi et al. Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature, 432, 488(2004).

    [24] K S Son, T S Kim, J S Jung et al. 4 inch QVGA AMOLED driven by the threshold voltage controlled amorphous GIZO (Ga2O3-In2O3-ZnO) TFT. SID Symp Dig Tech Pap, 39, 633(2008).

    [25] J H Lee, D H Kim, D J Yang et al. World’s largest (15-inch) XGA AMLCD panel using IGZO oxide TFT. SID Symp Dig Tech Pap, 39, 625(2008).

    [26] J S Park, T W Kim, D Stryakhilev et al. Flexible full color organic light-emitting diode display on polyimide plastic substrate driven by amorphous indium gallium zinc oxide thin-film transistors. Appl Phys Lett, 95, 013503(2009).

    [27] J S Park, J H Lim. 4-3: Invited paper: High mobility oxide thin-film transistors for AMOLED displays. SID Symp Dig Tech Pap, 53, 20(2022).

    [28] T Arai. Oxide-TFT technologies for next-generation AMOLED displays. J Soc Inf Disp, 20, 156(2012).

    [29] C L Lin, P C Lai, P C Lai et al. Pixel circuit with parallel driving scheme for compensating luminance variation based on a-IGZO TFT for AMOLED displays. J Disp Technol, 12, 1681(2016).

    [30] Y F Chen, S H Lee, H Kim et al. In-pixel temperature sensor for high-luminance active matrix micro-light-emitting diode display using low-temperature polycrystalline silicon and oxide thin-film-transistors. J Soc Inf Disp, 28, 528(2020).

    [31] D Cho, J Moon, T Y Kihm et al. 48-4: LTPO technology development for enhanced display performance: Image sticking phenomena, circuit operation and backplane process integration. SID Symp Dig Tech Pap, 53, 620(2022).

    [32] Y S Shiah, K Sim, Y H Shi et al. Mobility–stability trade-off in oxide thin-film transistors. Nat Electron, 4, 800(2021).

    [33] J L Shi, J Y Zhang, L Yang et al. Wide bandgap oxide semiconductors: From materials physics to optoelectronic devices. Adv Mater, 33, 2006230(2021).

    [34] J Y Noh, H Kim, H H Nahm et al. Cation composition effects on electronic structures of In-Sn-Zn-O amorphous semiconductors. J Appl Phys, 113, 183706(2013).

    [35] E Fortunato, P Barquinha, R Martins. Oxide semiconductor thin-film transistors: A review of recent advances. Adv Mater, 24, 2945(2012).

    [36] J Wallmark, H Johnson. Field-effect transistors: Physics, technology and applications. Prentice-Hall(1966).

    [37] L Petti, N Münzenrieder, C Vogt et al. Metal oxide semiconductor thin-film transistors for flexible electronics. Appl Phys Rev, 3, 021303(2016).

    [38] K Jang, J Raja, Y J Lee et al. Effects of carrier concentration, indium content, and crystallinity on the electrical properties of indium-tin-zinc-oxide thin-film transistors. IEEE Electron Device Lett, 34, 1151(2013).

    [39] S H Kim, C H Ahn, M G Yun et al. Anomalous tin chemical bonding in indium-zinc-tin oxide films and their thin film transistor performance. J Phys D: Appl Phys, 47, 485101(2014).

    [40] J Park, Y S Rim, C Li et al. Defect-induced instability mechanisms of sputtered amorphous indium tin zinc oxide thin-film transistors. J Appl Phys, 123, 161568(2018).

    [41] Z D Wu, H B Zhang, X L Wang et al. Effects of target quality on electrical performance and stability of In-Sn-Zn-O thin-film transistors. IEEE Electron Device Lett, 42, 529(2021).

    [42] J J Jia, Y Torigoshi, E Kawashima et al. Amorphous indium-tin-zinc oxide films deposited by magnetron sputtering with various reactive gases: Spatial distribution of thin film transistor performance. Appl Phys Lett, 106, 023502(2015).

    [43] T M Pan, B J Peng, J L Her et al. Effect of in and Zn content on structural and electrical properties of InZnSnO thin-film transistors using an Yb2TiO5 gate dielectric. IEEE Trans Electron Devices, 64, 2233(2017).

    [44] D H Lee, S Y Han, G S Herman et al. Inkjet printed high-mobility indium zinc tin oxide thin film transistors. J Mater Chem, 19, 3135(2009).

    [45] B J Kim, H J Kim, T S Yoon et al. Solution processed IZTO thin film transistor on silicon nitride dielectric layer. J Ind Eng Chem, 17, 96(2011).

    [46] R N Bukke, N N Mude, J K Saha et al. High performance of a-IZTO TFT by purification of the semiconductor oxide precursor. Adv Mater Interfaces, 6, 1900277(2019).

    [47] J Z Sheng, T Hong, D Kang et al. Design of InZnSnO semiconductor alloys synthesized by supercycle atomic layer deposition and their rollable applications. ACS Appl Mater Interfaces, 11, 12683(2019).

    [48] I H Baek, J J Pyeon, S H Han et al. High-performance thin-film transistors of quaternary indium–zinc–tin oxide films grown by atomic layer deposition. ACS Appl Mater Interfaces, 11, 14892(2019).

    [49] H Y Liu, W C Hsu, J H Chen et al. Amorphous ITZO thin-film transistors by using ultrasonic spray pyrolysis deposition. IEEE Trans Electron Devices, 67, 1009(2020).

    [50] R Li, S Q Dai, Y B Ma et al. High-performance transparent Li-doped indium-tin-zinc-oxide thin film transistor fabricated by radio frequency magnetron sputtering method. Mater Lett, 230, 132(2018).

    [51] R Li, S Q Dai, J B Su et al. Effect of thermal annealing on the electrical characteristics of an amorphous ITZO: Li thin film transistor fabricated using the magnetron sputtering method. Mater Sci Semicond Process, 96, 8(2019).

    [52] Y P Zhang, H Zhang, J Yang et al. Solution-processed yttrium-doped IZTO semiconductors for high-stability thin film transistor applications. IEEE Trans Electron Devices, 66, 5170(2019).

    [53] H B Zhang, L Y Liang, X L Wang et al. Praseodymium-doped In-Sn-Zn-O TFTs with effective improvement of negative-bias illumination stress stability. IEEE Trans Electron Devices, 69, 152(2022).

    [54] J J Jia, Y Torigoshi, A Suko et al. Effect of nitrogen addition on the structural, electrical, and optical properties of In-Sn-Zn oxide thin films. Appl Surf Sci, 396, 897(2017).

    [55] Z Y Li, H Z Yang, S C Chen et al. Impact of active layer thickness of nitrogen-doped In–Sn–Zn–O films on materials and thin film transistor performances. J Phys D: Appl Phys, 51, 175101(2018).

    [56] C S Fuh, P T Liu, W H Huang et al. Effect of annealing on defect elimination for high mobility amorphous indium-zinc-tin-oxide thin-film transistor. IEEE Electron Device Lett, 35, 1103(2014).

    [57] W Zhong, G Y Li, L F Lan et al. Effects of annealing temperature on properties of InSnZnO thin film transistors prepared by Co-sputtering. RSC Adv, 8, 34817(2018).

    [58] S Maeng, H Kim, G Choi et al. Investigation of electrical performance and operation stability of RF-sputtered InSnZnO thin film transistors by oxygen-ambient rapid thermal annealing. Semicond Sci Technol, 35, 125019(2020).

    [59] S Park, K Park, H Kim et al. Light-induced bias stability of crystalline indium-tin-zinc-oxide thin film transistors. Appl Surf Sci, 526, 146655(2020).

    [60] X L Wang, L Y Liang, H B Zhang et al. Huge mobility enhancement of InSnZnO thin-film transistors via Al-induced microstructure regularization. Appl Phys Lett, 119, 212102(2021).

    [61] G B Kim, N On, T Kim et al. High mobility IZTO thin-film transistors based on spinel phase formation at low temperature through a catalytic chemical reaction. Small Methods, 2201522(2023).

    [62] W H Tseng, S W Fang, C Y Lu et al. The effect of nitrous oxide plasma treatment on the bias temperature stress of metal oxide thin film transistors with high mobility. Solid State Electron, 103, 173(2015).

    [63] B H Wang, W Huang, L F Chi et al. High-k gate dielectrics for emerging flexible and stretchable electronics. Chem Rev, 118, 5690(2018).

    [64] Y G Bak, J W Park, Y J Park et al. In-Zn-Sn-O thin film based transistor with high-k HfO2 dielectric. Thin Solid Films, 753, 139290(2022).

    [65] K Jang, J Raja, J Kim et al. Bias-stability improvement using Al2O3 interfacial dielectrics in a-InSnZnO thin-film transistors. Semicond Sci Technol, 28, 085015(2013).

    [66] J Raja, C P T Nguyen, C M Lee et al. Improved data retention of InSnZnO nonvolatile memory by H2O2 treated Al2O3 tunneling layer: A cost-effective method. IEEE Electron Device Lett, 37, 1272(2016).

    [67] A Javey, H Kim, M Brink et al. High-κ dielectrics for advanced carbon-nanotube transistors and logic gates. Nat Mater, 1, 241(2002).

    [68] D B Ruan, P T Liu, Y C Chiu et al. Investigation of low operation voltage InZnSnO thin-film transistors with different high-k gate dielectric by physical vapor deposition. Thin Solid Films, 660, 885(2018).

    [69] R N Bukke, C Avis, M N Naik et al. Remarkable increase in field effect mobility of amorphous IZTO thin-film transistors with purified ZrOx gate insulator. IEEE Electron Device Lett, 39, 371(2018).

    [70] R N Bukke, N Naik Mude, J Lee et al. Effect of Hf alloy in ZrOx gate insulator for solution processed a-IZTO thin film transistors. IEEE Electron Device Lett, 40, 32(2019).

    [71] M Kim, H J Jeong, J Z Sheng et al. The impact of plasma-enhanced atomic layer deposited ZrSiOx insulators on low voltage operated In-Sn-Zn-O thin film transistors. Ceram Int, 45, 19166(2019).

    [72] W H Choi, W Jeon, J S Park. Nanoscale surface engineering of a high-k ZrO2/SiO2 gate insulator for a high performance ITZO TFT via plasma-enhanced atomic layer deposition. J Mater Chem C, 8, 13342(2020).

    [73] W Zhong, J F Zhang, Y Liu et al. Gate dielectric treated by self-assembled monolayers (SAMs) to enhance the performance of InSnZnO thin-film transistors. IEEE Trans Electron Devices, 69, 2398(2022).

    [74] C P T Nguyen, T T Trinh, J Raja et al. Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors. Mater Sci Semicond Process, 39, 649(2015).

    [75] J Park, M Shin, J Yi. Comparative study of aluminum and nickel contact electrodes for indium–tin–zinc oxide thin film transistors using oxygen vacancy diffusion model. Mater Sci Semicond Process, 120, 105253(2020).

    [76] S H Cho, Y U Lee, J S Lee et al. Effect of self-assembled monolayer (SAM) on the oxide semiconductor thin film transistor. J Disp Technol, 8, 35(2012).

    [77] W Zhong, G Y Li, L F Lan et al. InSnZnO thin-film transistors with vapor- phase self-assembled monolayer as passivation layer. IEEE Electron Device Lett, 39, 1680(2018).

    [78] W Zhong, R H Yao, Y Liu et al. Effect of self-assembled monolayers (SAMs) as surface passivation on the flexible a-InSnZnO thin-film transistors. IEEE Trans Electron Devices, 67, 3157(2020).

    [79] Y Y Chen, B Li, W Zhong et al. InSnZnO thin-film transistors with nitrogenous self-assembled multilayers passivation. IEEE Trans Electron Devices, 68, 5612(2021).

    [80] R N Bukke, C Avis, J Jang. Solution-processed amorphous In–Zn–Sn oxide thin-film transistor performance improvement by solution-processed Y2O3 passivation. IEEE Electron Device Lett, 37, 433(2016).

    [81] W Zhong, L Y Kang, S B Deng et al. Effect of Sc2O3 passivation layer on the electrical characteristics and stability of InSnZnO thin-film transistors. IEEE Trans Electron Devices, 68, 4956(2021).

    [82] Y H Shi, Y S Shiah, K Sim et al. High-performance a-ITZO TFTs with high bias stability enabled by self-aligned passivation using a-GaOx. Appl Phys Lett, 121, 212101(2022).

    [83] Y S Shiah, K Sim, S Ueda et al. Unintended carbon-related impurity and negative bias instability in high-mobility oxide TFTs. IEEE Electron Device Lett, 42, 1319(2021).

    [84] G J Jeon, J Yang, S H Lee et al. Abnormal thermal instability of Al-InSnZnO thin-film transistor by hydroxyl-induced oxygen vacancy at SiOx/active interface. IEEE Electron Device Lett, 42, 363(2021).

    [85] Z H Xia, L Lu, J P Li et al. Characteristics of elevated-metal metal-oxide thin-film transistors based on indium-tin-zinc oxide. IEEE Electron Device Lett, 38, 894(2017).

    [86] J Kim, D H Kim, S I Cho et al. Channel-shortening effect suppression of a high-mobility self-aligned oxide TFT using trench structure. IEEE Electron Device Lett, 42, 1798(2021).

    [87] J Lee, J D Jin, S Maeng et al. Enhancement of the electrical performance and bias stability of RF-sputtered indium tin zinc oxide thin-film transistors with vertical stoichiometric oxygen control. ACS Appl Electron Mater, 4, 1800(2022).

    [88] J D Jin, X Y Lin, J W Zhang et al. Low-voltage, high-performance, indium-tin-zinc-oxide thin-film transistors based on dual-channel and anodic-oxide. Adv Electron Mater, 9, 2201117(2023).

    [89] C P T Nguyen, J Raja, S Kim et al. Enhanced electrical properties of oxide semiconductor thin-film transistors with high conductivity thin layer insertion for the channel region. Appl Surf Sci, 396, 1472(2017).

    [90] M Lee, J W Jo, Y J Kim et al. Corrugated heterojunction metal-oxide thin-film transistors with high electron mobility via vertical interface manipulation. Adv Mater, 30, 1804120(2018).

    [91] W Yu, D Y Zhao, J Cai et al. Performance enhancement of TiZO thin film transistors by introducing a thin ITO interlayer. IEEE J Electron Devices Soc, 7, 1302(2019).

    Feilian Chen, Meng Zhang, Yunhao Wan, Xindi Xu, Man Wong, Hoi-Sing Kwok. Advances in mobility enhancement of ITZO thin-film transistors: a review[J]. Journal of Semiconductors, 2023, 44(9): 091602
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