A CMOS Voltage Reference with Second-Order Temperature Compensation Based on 65 nm CMOS Process

YANG Han; HOU Chenchen; ZHONG Ze; XIE Jiazhi; LIAO Shudan

doi:10.13911/j.cnki.1004-3365.200261

Journals >Microelectronics >Volume 51 >Issue 1 >Page 1 > Article

Microelectronics
Vol. 51, Issue 1, 1 (2021)

A CMOS Voltage Reference with Second-Order Temperature Compensation Based on 65 nm CMOS Process

YANG Han, HOU Chenchen, ZHONG Ze, XIE Jiazhi, and LIAO Shudan

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[in Chinese]

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DOI: 10.13911/j.cnki.1004-3365.200261 Cite this Article

YANG Han, HOU Chenchen, ZHONG Ze, XIE Jiazhi, LIAO Shudan. A CMOS Voltage Reference with Second-Order Temperature Compensation Based on 65 nm CMOS Process[J]. Microelectronics, 2021, 51(1): 1 Copy Citation Text

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References

[3] RAZAVI B. Design of analog CMOS integrated circuits ［M］. New York: McGraw-Hill Press, 2000: 377-399.

[4] BANBA H, SHIGA H, UMEZAWA A, et al. A CMOS bandgap reference circuit with sub-1 V operation ［J］. IEEE J Sol Sta Circ, 1999, 34(5): 670-674.

[5] PERRY R T, LEWIS S H, BROKAW A P, et al. A 1.4 V supply CMOS fractional bandgap reference ［J］. IEEE J Sol Sta Circ, 2007, 42(10): 2180-2186.

[6] ANNEMA A J, VELDHORST P, DOORNBOS G, et al. A sub-1 V bandgap voltage reference in 32 nm FinFET technology ［C］ // IEEE ISSCC. San Francisco, CA, USA. 2009: 332-333.

[7] MAGNELLI L, CRUPI F, CORSONELLO P, et al. A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference ［J］. IEEE J Sol Sta Circ, 2011, 46(2): 547-552.

[8] PAN J, INOUE Y. A sub-1-V low-voltage low-power voltage reference with a back-gate connection MOSFET ［C］ // Proceed IEEE ICCCAS. Guilin, China. 2006: 2314-2318.

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YANG Han, HOU Chenchen, ZHONG Ze, XIE Jiazhi, LIAO Shudan. A CMOS Voltage Reference with Second-Order Temperature Compensation Based on 65 nm CMOS Process[J]. Microelectronics, 2021, 51(1): 1

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