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Acta Photonica Sinica
Vol. 51, Issue 11, 1104002 (2022)

Effect of Transfer Gate Doping on Full Well Capacity and Dark Current in CMOS Active Pixels

Qian WANG, Jiangtao XU^*, Zhiyuan GAO, and Quanmin CHEN

Author Affiliations

Tianjin Key Laboratory of Imaging and Sensing Microelectronics，School of Microelectronics，Tianjin University，Tianjin 300072，China

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DOI: 10.3788/gzxb20225111.1104002 Cite this Article

Qian WANG, Jiangtao XU, Zhiyuan GAO, Quanmin CHEN. Effect of Transfer Gate Doping on Full Well Capacity and Dark Current in CMOS Active Pixels[J]. Acta Photonica Sinica, 2022, 51(11): 1104002 Copy Citation Text

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References

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[3] S RIZZOLO, V GOIFFON, M ESTRIBEAU et al. Influence of transfer gate design and bias on the radiation hardness of pinned photodiode CMOS image sensors. IEEE Transactions on Nuclear Science, 61, 3290-3301(2014).

[4] S RIZZOLO, V GOIFFON, M ESTRIBEAU et al. Influence of pixel design on charge transfer performances in CMOS image sensors. IEEE Transactions on Electron Devices, 65, 1048-1055(2018).

[5] SARKAR , MUKUL , BUTTGEN et al. Temperature effects on feedforward voltage in standard CMOS pinned photodiodes. IEEE Transactions on Electron Devices, 63, 1963-1968(2016).

[6] O MARCELOT, V GOIFFON, S RIZZOLO et al. Dark current sharing and cancellation mechanisms in CMOS image sensors analyzed by TCAD simulations. IEEE Transactions on Electron Devices, 64, 4985-4991(2017).

[7] B MHEEN, Y SONG, A J P THEUWISSEN. Negative offset operation of four-transistor CMOS image pixels for increased well capacity and suppressed dark current. IEEE Electron Device Letters, 29, 347-349(2008).

[8] T WATANABE, J H PARK, S AOYAMA et al. Effects of negative-bias operation and optical stress on dark current in CMOS image sensors. IEEE Transactions on Electron Devices, 57, 1512-1518(2010).

[9] W ZHANG, Z WEI, Y WANG et al. Investigation of CMOS image sensor dark current reduction by optimizing interface defect, 1-3(2017).

[10] J XU, Q CHEN, Z GAO. Analysis of transfer gate doping profile influence on dark current and FWC in CMOS image sensors. IEEE Journal of the Electron Devices Society, 9, 27-35(2021).

[11] E LIU, B ZHU, J LUO. The physics of semiconductors(2011).

[12] A PELAMATTI, V GOIFFON, M ESTRIBEAU et al. Estimation and modeling of the full well capacity in pinned photodiode CMOS image sensors. IEEE Electron Device Letters, 34, 900-902(2013).

[13] Y XU, A J P THEUWISSEN. Image lag analysis and photodiode shape optimization of 4T CMOS pixels, 153-157(2013).

[14] X WANG, P R RAO, A J P THEUWISSEN. Fixed-pattern noise induced by transmission gate in pinned 4T CMOS image sensor pixels, 331-334(2006).

[15] N KRAUSE, H SOLTAU, D HAUFF et al. Metal contamination analysis of the epitaxial starting material for scientific CCDs. Nuclear Instruments and Methods in Physics Research A, 439, 228-238(2000).

[16] H I KWON, I M KANG, B G PARK et al. The analysis of dark signals in the CMOS APS imagers from the characterization of test structures. IEEE Transactions on Electron Devices, 51, 178-184(2004).

[17] J R JANESICK, T ELLIOT, J ANDREWS et al. Fundamental performance differences of CMOS and CCD imagers: part V, 8659, 865902(2013).

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Qian WANG, Jiangtao XU, Zhiyuan GAO, Quanmin CHEN. Effect of Transfer Gate Doping on Full Well Capacity and Dark Current in CMOS Active Pixels[J]. Acta Photonica Sinica, 2022, 51(11): 1104002

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