Silicon photonics is promising for the demands of large-capacity data communications applications such as data centers, high-performance computers, and biomedical sensing [1,2]. One of the indispensable technologies in silicon photonics is high-speed signal detection for the near-infrared (∼1550nm), and germanium (Ge) is one of the most promising materials for near-infrared photodiodes (PDs) in optoelectronic integrated circuits due to its large absorption coefficient and compatibility with complementary metal-oxide-semiconductor (CMOS) technology [3]. Its superiority has led to substantial investigations of Ge PDs featuring high-frequency and responsivity in recent decades [4–10], while the parasitic parameters from either junction or electrodes limit a further increase in the bandwidth [11–13]. The Ge PDs can be divided into vertical and lateral positive-intrinsic-negative (PIN) junction structures. Although the bandwidth has achieved 120 GHz at −1V for lateral ones [7], the dark current is very large and the fabrication processes are complex, requiring silicon corrosion and a Ge chemical mechanical polish [14,15]. On the other hand, vertical PIN PDs enjoy great popularity, for their simple fabrication processes. However, they suffer from low bandwidth due to high parasitic parameters [16,17]. Therefore, the parasitic parameters are optimized in different ways to overcome these issues, such as shrinking the intrinsic region to reduce the junction capacitance [11], optimizing silicon doping to reduce the series resistance [18], and introducing spiral inductors in the electrodes to offset part of capacitance effect [5]. However, all of these reported schemes optimize the parasitic parameters separately, without comprehensively considering the relationships between different aspects. For instance, in Ref. [11], only the junction capacitance is reduced, and the bandwidth is still limited by series resistance and electrode parasitic parameters. In addition, they also suffer from optical responsivity degradation or fabrication complexity.

In this work, we propose and demonstrate a high-speed Ge vertical PIN PD, by comprehensively optimizing the parasitic parameters from both junction and electrodes. An equivalent circuit model containing transit time and all parasitic parameters is considered. The bandwidth limit under a given intrinsic region size is investigated through two-dimensional (2D) joint optimization, by varying the silicon doping concentration and electrodes inductance. Experimentally, the bandwidth is enhanced from 27 to 80 GHz, with a low dark current of 6.4 nA and an optical responsivity of 0.89 A/W, leading to a high detectivity. This is, to the best of our knowledge, the highest bandwidth of a CMOS-compatible vertical Ge PIN PD reported to date. This work provides guidance for the design of high-speed and high-detectivity Ge PDs.

The normalized frequency response of the radio frequency (RF) current through the load is shown in H(f)=11+j2πfRtCt·11+j2πfRpCj·11+j2πfRLCp,(1)where Rp=RL/(1+j2πRLCp)+Rs+j2πfLp.

As an implementation, the series resistance Rs can be changed effectively by the silicon P+ doping concentration calculated via the model in Ref. [22], as shown in Fig. 2(b). When the doping concentration increases, the resistance decreases until it reaches a constant of ∼50Ω for the given footprint of silicon we adopted. The resistance of P+ doped silicon will not be further reduced until ∼10Ω, considering that the impurities cannot be completely ionized at a sufficiently high doping concentration [22]. The minimum of Rs is mainly limited by the unchanged silicon-metal contact resistance of ∼40Ω [18]. Based on the analyses above, the full P++ doping is used in the whole silicon layer to minimize the resistance. On the other hand, for conventional ground-source-ground (GSG) electrodes, the Lp is very small and can be significantly enlarged by introducing inductors of different lengths to generate a gain peaking effect [5,6]. When the inductance is about 240 pH, the bandwidth limit is ∼85GHz for the minimum series resistance of 50 Ω, signed in Fig. 2(a). Note that other parasitic parameters remain almost unchanged for a fixed intrinsic region size, and it is reasonable to perform the 2D optimization for Rs and Lp. Thus, the theoretical limit can be obtained compared to the individual optimization.

The PDs are fabricated using an SOI wafer with an 220 nm thick silicon top layer and a 2 μm buried oxide (BOX). The grating coupler is first etched 70 nm from 220 nm silicon layer. After that, the silicon layer is etched into a ridge waveguide with a 90 nm slab for better light constraints. Then, the silicon top layer is P++ or P+ doping using different doses of boron. A 500 nm thick germanium is deposited on the doping region of the silicon, and ∼100nm depth N++ doping of phosphorus is implanted on top of the Ge to form the vertical PIN junction. The area of the Ge is 5 μm wide and 10 μm in length. The first via and metal to N++ Ge and P++ silicon are fabricated; subsequently, the second via and metal are fabricated to form different inductors. PD-A, PD-B, and PD-REF were fabricated on the same wafer and at the same time.

Small-signal RF measurements are carried out using a 67 GHz vector network analyzer (VNA: MS4647B, Anritsu Corp., Kanagawa, Japan) in the test range of 10 MHz to 70 GHz with 50 Ω load resistance. The impedance standard substrate [101-190C, FormFactor (formerly Cascade Microtech), Beaverton, OR, USA] is used to calibrate the bias-tee, cables, and microprobe (I67-GSG-150, FormFactor).

To fairly characterize the proposed PDs, we take advantage of the concept of detectivity (D*), which is calculated using [24] D*=RAΔfIshot2+Ither2,(2)where R is the responsivity, Δf is the unit bandwidth (1 Hz), Ishot is the shot noise, and Ither is the thermal noise. Ishot and Ither can be expressed as Ishot=2qIdarkΔf,(3)Ither=4kTΔfRshunt,(4)where Idark is the dark current and Rshunt is the shunt resistance, which is extracted by taking dI/dV at V=0. It can be seen from Eq. (2) that D* includes both the responsivity and the dark current, and it is a more suitable metric to characterize the comprehensive performance of the PD. A higher responsivity and a lower dark current can lead to a higher D*. Table 3 summarizes the comparison of the high-speed waveguide-coupled Ge PDs in literature and our work. The latter has the best detectivity, thanks to the ultralow dark current and highest responsivity. The bandwidth is also the highest among the reported vertical Ge PDs using conventional fabrication processes. Although Ref. [7] demonstrated a bandwidth as high as 120 GHz, the process is complex (requiring silicon corrosion and a Ge chemical mechanical polish) and the dark current is large, resulting in a ∼15× lower detectivity. We believe the proposed work is very attractive for applications such as a high-speed data communications system, considering the high-performance and zero-change fabrication process in the standard silicon photonics platform.Table 3.

Comparison of the High-Speed Waveguide-Coupled Ge PDs

We have demonstrated that 2D parasitic parameter engineering enables a significant bandwidth boost for Ge PDs. The bandwidth is experimentally enhanced from 27 to 80 GHz, and approaches the limit of 82 GHz. This method does not cause a degradation in responsivity and the dark current, which results in a very high detectivity. We believe it will pave the way toward the design of high-speed, high-detectivity Ge PDs.