• Journal of Semiconductors
  • Vol. 44, Issue 12, 124101 (2023)
Zhenzhen Kong1、4, Hongxiao Lin3、4, Hailing Wang2, Yanpeng Song2, Junjie Li1, Xiaomeng Liu2, Anyan Du1, Yuanhao Miao1、3, Yiwen Zhang1、4, Yuhui Ren1、4, Chen Li1、4, Jiahan Yu1、4, Jinbiao Liu1、4, Jingxiong Liu1、4, Qinzhu Zhang1, Jianfeng Gao1, Huihui Li2, Xiangsheng Wang2, Junfeng Li1, Henry H. Radamson3, Chao Zhao2, Tianchun Ye1、4, and Guilei Wang2、5、*
Author Affiliations
  • 1Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  • 2Beijing Superstring Academy of Memory Technology, Beijing 100176, China
  • 3Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China
  • 4Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, China
  • 5Hefei National Laboratory, Hefei 230088, China
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    DOI: 10.1088/1674-4926/44/12/124101 Cite this Article
    Zhenzhen Kong, Hongxiao Lin, Hailing Wang, Yanpeng Song, Junjie Li, Xiaomeng Liu, Anyan Du, Yuanhao Miao, Yiwen Zhang, Yuhui Ren, Chen Li, Jiahan Yu, Jinbiao Liu, Jingxiong Liu, Qinzhu Zhang, Jianfeng Gao, Huihui Li, Xiangsheng Wang, Junfeng Li, Henry H. Radamson, Chao Zhao, Tianchun Ye, Guilei Wang. Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM[J]. Journal of Semiconductors, 2023, 44(12): 124101 Copy Citation Text show less
    References

    [1] H H Radamson, H L Zhu, Z H Wu et al. State of the art and future perspectives in advanced CMOS technology. Nanomaterials (Basel), 10, 1555(2020).

    [2] H H Radamson, E Simeon. CMOS past, present and future. Amsterdam: Elsevier, 105(2018).

    [3] N Loubet, S Kal, C Alix et al. A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around NanoSheet devices(2020).

    [4] H H Radamson, Y B Zhang, X B He et al. The challenges of advanced CMOS process from 2D to 3D. Appl Sci, 7, 1047(2017).

    [5] H H Radamson, X B He, Q Z Zhang et al. Miniaturization of cmos. Micromachines, 10, 293(2019).

    [6] H H Radamson, K B Joelsson, W X Ni et al. Characterization of highly boron-doped Si, Si1−xGex and Ge layers by high-resolution transmission electron microscopy. J Cryst Growth, 157, 80(1995).

    [7] G L Wang, J Luo, C L Qin et al. Integration of highly strained SiGe in source and drain with HK and MG for 22 nm bulk PMOS transistors. Nanoscale Res Lett, 12, 123(2017).

    [8] N Singh, K D Buddharaju, S K Manhas et al. Si, SiGe nanowire devices by top–down technology and their applications. IEEE Trans Electron Devices, 55, 3107(2008).

    [9] S Barraud, B Previtali, V Lapras et al. Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies. Semicond Sci Technol, 34, 074001(2019).

    [10] H H Radamson, M Kolahdouz. Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs. J Mater Sci: Mater Electron, 26, 4584(2015).

    [11] C L Chu, K Wu, G L Luo et al. Stacked Ge-nanosheet GAAFETs fabricated by Ge/Si multilayer epitaxy. IEEE Electron Device Lett, 39, 1133(2018).

    [12] A Veloso, V Paraschiv, E Vecchio et al. (invited) challenges on surface conditioning in 3D device architectures: Triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs. ECS Trans, 80, 3(2017).

    [13] M Neisser. International roadmap for devices and systems lithography roadmap. J Micro/nanopatterning Mater Metrol, 20, 44601(2021).

    [14] D Ha, H S Kim. Prospective innovation of DRAM, flash, and logic technologies for digital transformation (DX) era, 417(2022).

    [15] M Huang, S F Si, Z He et al. A 3D stackable 1T1C DRAM: Architecture, process integration and circuit simulation, 1(2023).

    [16] J W Han, S H Park, M Y Jeong et al. Ongoing evolution of DRAM scaling via third dimension-vertically stacked DRAM, 1(2023).

    [17] S Rachidi, A Campo, V Loup et al. Isotropic dry etching of Si selectively to Si0.7Ge0.3 for CMOS sub-10 nm applications. J Vac Sci Technol A Vac Surf Films, 38, 033002(2020).

    [18] T Huynh-Bao, S Sakhare, D Yakimets et al. A comprehensive benchmark and optimization of 5-nm lateral and vertical GAA 6T-SRAMs. IEEE Trans Electron Devices, 63, 643(2016).

    [19] Y C Liu, C T Tu, C E Tsai et al. First highly stacked Ge0.95Si0.05 nGAAFETs with record ION = 110 μA (4100 μA/μm) at VOV=VDS=0.5V and high Gm, max = 340 μS (13000 μS/μm) at VDS=0.5V by wet etching, 1(2021).

    [20] J J Li, W W Wang, Y L Li et al. Study of selective isotropic etching Si1−xGex in process of nanowire transistors. J Mater Sci:Mater Electron, 31, 134(2020).

    [21] S Lee, J Jeong, J S Yoon et al. Sensitivity of inner spacer thickness variations for sub-3-nm node silicon nanosheet field-effect transistors. Nanomaterials, 12, 3349(2022).

    [22] S Reboh, R Coquand, S Barraud et al. Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology. Appl Phys Lett, 112, 051901(2018).

    [23] C G Tuppen, C J Gibbings, M Hockly. Mismatch dislocation nucleation and propagation in Si/Si1−xGex heterostructures. MRS Proc, 130, 185(1988).

    [24] L Barbisan, A Marzegalli, F Montalenti. Atomic-scale insights on the formation of ordered arrays of edge dislocations in Ge/Si(001) films via molecular dynamics simulations. Sci Rep, 12, 3235(2022).

    [25] M Orlowski, C Ndoye, T Liu et al. (invited) Si, SiGe, Ge, and III-V semiconductor nanomembranes and nanowires enabled by SiGe epitaxy. ECS Trans, 33, 777(2010).

    [26] S Borel, C Arvet, J Bilde et al. Isotropic etching of SiGe alloys with high selectivity to similar materials. Microelectron Eng, 73/74, 301(2004).

    [27] V Caubet, C Beylier, S Borel et al. Mechanisms of isotropic and selective etching between SiGe and Si. J Vac Sci Technol B Microelectron Nanometer Struct Process Meas Phenom, 24, 2748(2006).

    [28] Y Zhao, T Iwase, M Satake et al. Formation mechanism of rounded SiGe-etch front in isotropic SiGe plasma etching for gate-all-around FETs. IEEE J Electron Devices Soc, 9, 1112(2021).

    [29] W Y Chang, G L Luo, Y S Huang et al. SiGe and Si gate-all-around FET fabricated by selective etching the same epitaxial layers, 21(2022).

    [30] K Wostyn, F Sebaai, J Rip et al. (invited) selective etch of Si and SiGe for gate all-around device architecture. ECS Trans, 69, 147(2015).

    [31] Y Choi, H Jang, D S Byun et al. Selective chemical wet etching of Si1-xGex versus Si in single-layer and multi-layer with HNO3/HF mixtures. Thin Solid Films, 709, 138230(2020).

    [32] S Kim, M Kim, D Ryu et al. Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet gate-all-around MOSFETs. IEEE Trans Electron Devices, 67, 2648(2020).

    [33] J Zhuge, R S Wang, R Huang et al. Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology, 1(2010).

    [34] S A Sous, B O Hildmann, W A Kaysser. Characterization of dislocation densities in germanium and silicon single crystals by high resolution X-ray diffraction. Phys Stat Sol (a), 159, 343(1997).

    [35] H H Radamson, M Moeen, A Abedin et al. Sensitivity of signal-to-noise ratio to the layer profile and crystal quality of SiGe/Si multilayers. ECS J Solid State Sci Technol, 5, P3196(2016).

    [36] J M Hartmann, A M Papon, J P Barnes et al. Growth kinetics of SiGe/Si superlattices on bulk and silicon-on-insulator substrates for multi-channel devices. J Cryst Growth, 311, 3152(2009).

    [37] H H Radamson, J Hållstedt. Application of high-resolution X-ray diffraction for detecting defects in SiGe(C) materials. J Phys: Condens Matter, 17, S2315(2005).

    [38] V Destefanis, J M Hartmann, M Hopstaken et al. Low-thermal surface preparation, HCl etch and Si/SiGe selective epitaxy on (1 1 0) silicon surfaces. Semicond Sci Technol, 23, 105018(2008).

    [39] N Loubet, T Kormann, G Chabanne et al. Selective etching of Si1−xGex versus Si with gaseous HCl for the formation of advanced CMOS devices. Thin Solid Films, 517, 93(2008).

    [40] H Mertens, R Ritzenthaler, A Hikavyy et al. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates, 1(2016).

    [41] Y H Tsai, M M Wang. Fundamental study on the selective etching of SiGe and Si in ClF3 gas for nanosheet gate-all-around transistor manufacturing: A first principle study. J Vac Sci Technol B, 40, 013201(2022).

    [42] C Catano, N Joy, C Talone et al. Peculiarities of selective isotropic Si etch to SiGe for nanowire and GAA transistors. SPIE Advanced Lithography. Proc SPIE 10963, Advanced Etch Technology for Nanopatterning VIII, 1096, 72(2019).

    [43] T K Cams, M O Tanner, K L Wang. Chemical etching of Si1–xGex in HF : H2O2: CH3COOH. J Electrochem Soc, 142, 1260(1995).

    [44] B Holländer, D Buca, S Mantl et al. Wet chemical etching of Si, Si1–xGex, and Ge in HF: H2O2: CH3COOH. J Electrochem Soc, 157, H643(2010).

    [45] A Pacco, Z Tao, J Rip et al. Scaled-down c-Si and c-SiGe wagon-wheels for the visualization of the anisotropy and selectivity of wet-chemical etchants. Nanoscale Res Lett, 14, 1(2019).

    [46] Z Baraissov, A Pacco, S Koneti et al. Selective wet etching of silicon germanium in composite vertical nanowires. ACS Appl Mater Interfaces, 11, 36839(2019).

    [47] X G Yin, H L Zhu, L H Zhao et al. Study of isotropic and Si-selective quasi atomic layer etching of Si1–xGex. ECS J Solid State Sci Technol, 9, 034012(2020).

    [48] Y Y Li, H L Zhu, Z Z Kong et al. The effect of doping on the digital etching of silicon-selective silicon–germanium using nitric acids. Nanomaterials, 11, 1209(2021).

    Zhenzhen Kong, Hongxiao Lin, Hailing Wang, Yanpeng Song, Junjie Li, Xiaomeng Liu, Anyan Du, Yuanhao Miao, Yiwen Zhang, Yuhui Ren, Chen Li, Jiahan Yu, Jinbiao Liu, Jingxiong Liu, Qinzhu Zhang, Jianfeng Gao, Huihui Li, Xiangsheng Wang, Junfeng Li, Henry H. Radamson, Chao Zhao, Tianchun Ye, Guilei Wang. Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM[J]. Journal of Semiconductors, 2023, 44(12): 124101
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