A Method of Calibrating Interstage Gain of Pipeline A/D Converter by Piecewise Shift Technique

LEI Langcheng; WANG Zhongyan; ZHAN Yong; LIU Honghong; HU Yongfei; DU Yubin; FU Dongbing

doi:10.13911/j.cnki.1004-3365.220108

[3] TSENG C J, CHEN H W, SHEN W T, et al. A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC ［J］. IEEE J Sol Sta Circ, 2012, 47(6): 1334-1343.

[4] ALI A M A, MORGAN A, DILLON C, et al. A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration ［J］. IEEE J Sol Sta Circ, 2010, 45(12): 2602-2612.

[5] AHMED I, JOHNS D A. An 11-bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage ［J］. IEEE J Sol Sta Circ, 2008, 43(7): 1626-1637.

[6] ALI A M A, HUSERIN D, PARITOSH B, et al. A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration ［J］. IEEE J Sol Sta Circ, 2014, 49(12): 2857- 2867.

[7] ZHONG J Y, ZHU Y, SIN S W, et al. Inter-stage gain error self-calibration of a 31.5 fJ 10 b 470 MSPS pipelined-SAR ADC ［C］// IEEE ASSCC. Kobe, Japan. 2012: 153-156.

[8] MOHAMMAD T S, HAMOUI A A. Digital background calibration of capacitor-mismatch errors in pipelined ADCs ［J］. IEEE J Sol Sta Circ, 2006, 53(9): 966-970.

[9] MIYAHARA Y, SNAO M , KOYAMA K, et al. A 14 b 60 MS/s pipelined ADC adaptively cancelling opamp gain and nonlinearity ［J］. IEEE J Sol Sta Circ, 2014, 49(2): 416-425.