The gain mismatch between sampling capacitance and feedback capacitance in pipeline A/D converters was analyzed. The relationship between the finite gain of operational amplifier and pipeline residual output, as well as the output of A/D converter, was investigated. So an accurate system model was established. Based on the Verilog-A behavioral model of 14 bit pipelined ADC, the digital output of pipelined ADC was shifted piecewisely in digital domain. When the inter-stage gain error of first stage reached ±0.012 5, the SNR was only 62 dB before calibration, and it was 85 dB after calibration. The proposed calibration method could compensate for the discontinuity of digital output and the linearity degeneration caused by inter-stage gain errors.