HRM: H-tree based reconfiguration mechanism in reconfigurable homogeneous PE array

Junyong Deng; Lin Jiang; Yun Zhu; Xiaoyan Xie; Xinchuang Liu; Feilong He; Shuang Song; L. K. John

doi:10.1088/1674-4926/41/2/022402

Journals >Journal of Semiconductors >Volume 41 >Issue 2 >Page 022402 > Article

Journal of Semiconductors
Vol. 41, Issue 2, 022402 (2020)

HRM: H-tree based reconfiguration mechanism in reconfigurable homogeneous PE array

Junyong Deng¹, Lin Jiang², Yun Zhu¹, Xiaoyan Xie³, Xinchuang Liu¹, Feilong He³, Shuang Song⁴, and L. K. John⁴

Author Affiliations

¹School of Electronic Engineering, Xi’an University of Posts & Telecommunications, Xi’an 710121, China

²School of Communication and Information Engineering, Xi’an University of Science and Technology, Xi’an 710054, China

³School of Computer, Xi’an University of Posts & Telecommunications, Xi’an 710121, China

⁴The University of Texas at Austin, TX 78712, USA

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DOI: 10.1088/1674-4926/41/2/022402 Cite this Article

Junyong Deng, Lin Jiang, Yun Zhu, Xiaoyan Xie, Xinchuang Liu, Feilong He, Shuang Song, L. K. John. HRM: H-tree based reconfiguration mechanism in reconfigurable homogeneous PE array[J]. Journal of Semiconductors, 2020, 41(2): 022402 Copy Citation Text

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Fig. 1. (Color online) The topology of HRM. (a) Unicast. (b) Multicast/broadcast.

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Fig. 2. (Color online) Homogeneous thin-core PE array. (a) Inter –cluster communicate. (b) PE cluster. (c) Micro-architecture of PE.

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Fig. 3. (Color online) Distributed shared memory structure.

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Fig. 4. (Color online) The prototype system of the proposed approach.

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Fig. 5. (Color online) Organizations of video processing system. (a) Original organization of video processing system. (b) Video processing system with higher parallelism.

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Fig. 6. Results of different sequences in video processing. (a) Salesman. (b) Bridge.

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Fig. 7. Mapping of viewport transportation.

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Fig. 8. (Color online) Rendering scene by proposed scheme.

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Fig. 9. Data-driven mode mapping of six-tap filter. (a) Six-tap filter. (b) Data-driven mode mapping.

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Component	Parameter	This paper	RSF
PE	Bit-width of regs in a PE	16	16
	# of regs in a PE	16	4
	# of PEs	16	16
CM(4 kB)/IM(1 kB)	Bit-width of a CM/IM	32	32
CM(4 kB)/IM(1 kB)	# of CMs/IMs	16	16
CB(1.5 kB)/DRAM(512 B)	# of sets	1	2
	# of banks in a set	1	3
	Bit-width of a bank	16	32

Table 1. PE cluster RTL implementation.

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FU changing	PE	Operation instruction	Call instruction
DCT→Intra	16→2	2856	8
DB→Intra	15→8	2087	9
Intra→DB	9→12	2584	8
IME→DCT	11→16	3136	7
FME→IME	2→11	39	16
FME	2	0	2
MC	5	0	5

Table 2. The statistics of reconfiguration instructions.

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Comparison aspect	PE cluster				HRM
Comparison aspect	This paper	RSF	HReA	Comparison	HRM
Process (nm)	90	90	65	—	90
Area (gate equivalent)	4155696	6586491	—	36.9%↓	4331
Critical delay (ns)	2.80	3.74	3.57	25.1%↓, 21.6%↓	2.02
Power (mW)	1.96	0.8	—	145%↑	0.48

Table 3. Synthesis results of PE cluster.

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