• Microelectronics
  • Vol. 51, Issue 1, 85 (2021)
PENG Jiahao1、2, LI Ruzhang2, FU Dongbing2, DING Yi2, and YANG Hong1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.200059 Cite this Article
    PENG Jiahao, LI Ruzhang, FU Dongbing, DING Yi, YANG Hong. A 12.5 Gbit/s High Speed SerDes Transmitter Based on Differential Encoding Technology[J]. Microelectronics, 2021, 51(1): 85 Copy Citation Text show less
    References

    [1] HARWOOD M, NIELSEN S, SZCZEPANEK A, et al. A 225 mW 28 Gb/s SerDes in 40 nm CMOS with 13 dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications [C] // IEEE ISSCC. San Francisco, CA, USA. 2012: 326-327.

    [2] CHEN M S, SHIH Y N, LIN C L, et al. A fully-integrated 40-Gb/s transceiver in 65-nm CMOS technology [J]. IEEE J Sol Sta Circ, 2012, 47(3): 627-640.

    [3] NAVID R, CHEN E H, HOSSAIN M, et al. A 40 Gb/s serial link transceiver in 28 nm CMOS technology [J]. IEEE J Sol Sta Circ, 2015, 50(4): 814-827.

    [4] KIM T, JANG S, KIM S, et al. A four-channel 32-Gb/s transceiver with current-recycling output driver and on-chip AC coupling in 65-nm CMOS process [J]. IEEE Trans Circ Syst II Expr Brie, 2014, 61(5): 304-308.

    [5] YOU L, FENG Z, LV J, et al. A 5 Gb/s multi-mode transmitter with de-emphasis for PCI Express 2.0/USB 3.0 [J]. Analog Integr Circ Signal Process, 2014, 81(2): 503-513.

    [6] CHOI K W, BLACKSHEAR E, TREMBLE E, et al. Hybrid prepreg conventional build-up laminate for 112 Gbit/s SerDes [C] // IEEE 69th ECTC. Las Vegas, NV, USA. 2019, 1179-1187.

    [7] PANDEY N, GUPTA K, BHATIA G, et al. MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells [J]. Microelec J, 2016, 57(C): 13-20.

    [8] FUKUDA K, YAMASHITA H, ONO G, et al. A 12.3-mW 12.5-Gb/s complete transceiver in 65-nm CMOS process [J]. IEEE J Sol Sta Circ, 2010, 45(12): 2838-2849.

    [9] JEDEC Solid State Technology Association. JEDEC Standard JESD204B [EB/OL]. https://www.jedec. org, 2011.

    [10] BIDAJ K, BEGUERET J B, DEROO J. Jitter definition, measurement, generation, analysis, and decomposition [J]. Int J Circ Theory Appl, 2018, 46(12): 2171-2188.

    PENG Jiahao, LI Ruzhang, FU Dongbing, DING Yi, YANG Hong. A 12.5 Gbit/s High Speed SerDes Transmitter Based on Differential Encoding Technology[J]. Microelectronics, 2021, 51(1): 85
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