A Novel Security Evaluation Method for Cryptographic Chip

YANG Xue; ZHANG Chi; SHAN Weijun; WANG Lihui; LI Qing; YU Jun

doi:10.13911/j.cnki.1004-3365.200386

[1] KOCHER P C. Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems ［C］ // 16th CRYPTO. Santa Barbara, CA, USA. 1996: 104-113.

[3] BIRYUKOV A, CANNIERE C D. Data encryption standard (DES) ［J］. Encyclopedia Cryptography & Security, 2011, 28(2): 295-301.

[5] KOCHER P C, JAFFE J, JUN B. Differential power analysis ［C］ // 19th CRYPTO. Santa Barbara, CA, USA. 1999: 388-397.

[6] BRIER E, CLAVIER C, OLIVIER F. Correlation power analysis with a leakage model ［C］ // CHES. Cambridge, MA, USA. 2004: 16-29.

[8] SCHNEIDER T, MORADI A. Leakage assessment methodology ［J］. J Cryptographic Engineer, 2016, 6(2): 85-99.

[9] IEEE standard for Verilog hardware description language: IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001) ［S］. IEEE, 2006.

[10] GROB H, MANGARD S, KORAK T. An efficient side-channel protected AES implementation with arbitrary protection order ［C］ // CT-RSA. San Francisco, CA, USA. 2017: 95-112.

[11] SHAN W, WANG L, LI Q, et al. A chosen-plaintext method of CPA on SM4 block cipher ［C］ // IEEE 10th Int Conf Computational Intelligence and Security. Kunming, China. 2014: 363-366.