Contents
2021
Volume: 51 Issue 3
28 Article(s)
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Design of a High-Performance Residue Amplifier for Pipelined-SAR ADC Based on gm/Id Methodology
RAO Chenguang, XIAO Rui, SANG Qinghua, and DENG Honghui
Based on the gm/Id lookup table methodology, a residue amplifier for a 14-bit 100 MS/s pipelined successive approximation register analog-to-digital converter (Pipelined-SAR ADC) was designed. The residue amplifier used a high-gain and wide-bandwidth gain-boosted operational amplifier (OTA) structure. The methodology uBased on the gm/Id lookup table methodology, a residue amplifier for a 14-bit 100 MS/s pipelined successive approximation register analog-to-digital converter (Pipelined-SAR ADC) was designed. The residue amplifier used a high-gain and wide-bandwidth gain-boosted operational amplifier (OTA) structure. The methodology used a lookup function to find the DC operating point of the devices, which overcame the problem that the conventional method could not accurately design the parameters of the short channel devices. Through the iterative algorithm to select the gm/Id of the core devices, the circuit could achieve optimal design of power consumption while meeting the performance requirements, and had a nice process portability. The OTA performance of the design was simulated and verified in SMIC 55 nm CMOS process. The optimized design of the circuit power consumption of 1.9 mW under the multi-dimensional constraints such as a DC gain of 92 dB, a closed-loop -3 dB bandwidth of 180 MHz and a noise (rms) of 1.44 mV was realized..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 295 (2021)
A New Charge Pump Regulation Technology for Flash Memory
XIONG Li, and HUANG Lu
The charge pump is an important circuit module for programming, erasing and reading in flashs and EEROMs. The pump regulator circuit is used to output stable voltages and currents. In this paper, a pump regulator circuit was proposed to solve the problem of larger ripple in the traditional circuit at light load, which The charge pump is an important circuit module for programming, erasing and reading in flashs and EEROMs. The pump regulator circuit is used to output stable voltages and currents. In this paper, a pump regulator circuit was proposed to solve the problem of larger ripple in the traditional circuit at light load, which was difficult to be applied to multi-bit flash. The characteristics of the circuit were that a clock amplitude adjustment module was added to traditional frequency adjustment circuit. So the pump worked at a smaller clock amplitude under light load, and at a maximum amplitude under heavy load. A latch controller prevented the clock amplitude from changing repeatedly. Based on XMC 65 nm FG process, the circuit was simulated by Cadence Spectre. The results showed that the ripple voltage was about 40 mV under both light and heavy load, which effectively reduced the ripple under light load conditions..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 303 (2021)
A Low Voltage Self-Starting Circuit for Thermoelectric Energy Harvesting
CUI Peng, WEI Baolin, LIANG Zhanrong, XUAN Yan, XU Weilin, WEI Xueming, and DUAN Jihai
A two-stage low voltage self-starting circuit was designed for thermoelectric energy collection systems under low input voltages. A novel stacked inverter was introduced in the first stage to form a ring oscillator that could be used to generate large oscillation amplitudes at low supply voltages. The second stage consA two-stage low voltage self-starting circuit was designed for thermoelectric energy collection systems under low input voltages. A novel stacked inverter was introduced in the first stage to form a ring oscillator that could be used to generate large oscillation amplitudes at low supply voltages. The second stage consisted of a high-amplitude clock generation circuit and a multiplexing-inductor boost circuit, further enhancing the output voltage. The control circuit, which was constituted by voltage detection circuits and auxiliary circuits, realized the transition from the first stage to the second and from the second stage to the main boost. The circuit was design in a 0.18 μm CMOS process. As shown by the results of the post-layout simulation, at a TEG input voltage of 190 mV and a load current of 11.8 μA, the circuit could generate an output voltage of 825 mV with a conversion efficiency of 56.5%. Self-starting was realized in the energy collection system, guaranteeing the normal operations of the post-stage main boost circuits..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 308 (2021)
A 77 GHz Power Amplifier Based on 0.13 μm SiGe Process
HUANG Jiwei, and ZHU Jiaxin
A 77 GHz power amplifier based on a 0.13 μm SiGe process was presented. A two-way combined structure was used to increase the output power, and a two-stage differential structure was used to increase the gain. The cascode structure was selected for the power stage to improve the output impedance and facilitate the matcA 77 GHz power amplifier based on a 0.13 μm SiGe process was presented. A two-way combined structure was used to increase the output power, and a two-stage differential structure was used to increase the gain. The cascode structure was selected for the power stage to improve the output impedance and facilitate the matching. The structure of common emitter stage with neutralizing capacitor was selected for the drive stage to increase the gain. Two pairs of differential signals were obtained from the input through the Balun power divider of two-way coupled lines, which were amplified by two channels, and were output by the combination of Balun power combiner of two-way coupled lines. Transformer matching was adopted for inter-stage matching. The proposed power amplifier was simulated by the ADS software. Simulation results showed that the small signal gain was 19.6 dB, the peak power additional efficiency was 11%, and the saturated output power was 18.5 dBm at 77 GHz..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 314 (2021)
A Low Power Hysteresis Comparator Suitable for Energy Harvesting System
LIANG Zhanrong, WEI Baolin, CUI Peng, XUAN Yan, XU Weilin, WEI Xueming, YUE Hongwei, and DUAN Jihai
According to the application requirements of the weak energy harvesting system, a folded low voltage, low power hysteresis comparator with a wide voltage range was designed. In the input stage and output stage of the comparator, the biasing circuit and internal node were used to bias the tail transistors respectively, According to the application requirements of the weak energy harvesting system, a folded low voltage, low power hysteresis comparator with a wide voltage range was designed. In the input stage and output stage of the comparator, the biasing circuit and internal node were used to bias the tail transistors respectively, which realized the automatic adjustment of the tail current according to the variation of the practical working voltage. So the power consumption and the output response time were decreased. Based on a 0.18 μm CMOS process, the simulation results showed that the comparator could work normally in the range of 0.8~1.2 V supply voltage, the hysteresis voltage was adjustable in the range of 15~70 mV, and the lowest power consumption was 0.15 μW..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 319 (2021)
A 7~13 GHz Low Insertion Loss 6 bit Digital Attenuator
ZHAI Yinghui, WAN Jing, LIN Fujiang, YE Tianchun, YAN Yuepeng, and LIANG Xiaoxin
A six-bit digital attenuator with low insertion loss was designed in a 0.25 μm GaAs p-HEMT process. The Pi-type attenuation structure and the T-type attenuation structure were cascaded to achieve low insertion loss and high attenuation accuracy. The phase shift compensation circuit was used to reduce the additional phaA six-bit digital attenuator with low insertion loss was designed in a 0.25 μm GaAs p-HEMT process. The Pi-type attenuation structure and the T-type attenuation structure were cascaded to achieve low insertion loss and high attenuation accuracy. The phase shift compensation circuit was used to reduce the additional phase shift, and the amplitude compensation circuit was used to improve the attenuation accuracy. The simulation results showed that the RMS amplitude error was less than 0.5 dB, and the insertion loss was less than 5.6 dB in the range of 7~13 GHz. The input 1 dB compression point was about 29 dBm at 10 GHz, the additional phase shift was -7°~+6.5°, and the input/output return loss was less than -11 dB. The chip area was 2.50 mm×0.63 mm..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 324 (2021)
Design of a New High Efficiency and High Voltage Synchronous Rectifier Circuit
HE Xudong, DENG Yaxu, and CHEN Yongyi
A synchronous rectifier circuit for AC-DC power adaptor was designed, which integrated synchronous rectifier control chips, power MOSFETs and energy storage capacitors. The new rectifier circuit could quickly and accurately switch the power MOSFET without external power supply, external drive signal and external componA synchronous rectifier circuit for AC-DC power adaptor was designed, which integrated synchronous rectifier control chips, power MOSFETs and energy storage capacitors. The new rectifier circuit could quickly and accurately switch the power MOSFET without external power supply, external drive signal and external components. So the synchronous rectification function was realized. Compared with the traditional Schottky rectifier circuits, this rectifier circuit had higher efficiency, fewer peripheral devices and wider application range. The synchronous rectifier chip was designed and realized in a 0.35 μm high voltage CMOS process. The results showed that the measured average efficiency of the rectifier circuit was 3% higher than that of the traditional circuit under the AC input voltage of 220 V, the output voltage of 5 V and the maximum load current of 5 A..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 330 (2021)
Design of a High-Precision Calibration Circuit for On-chip Resistances
WEI Xueming, XIONG Xiaohui, and HOU Lingli
A high precision on-chip resistance calibration circuit with the adjustment range of 40 Ω to 100 Ω was designed, which could accurately calibrate the on-chip resistance value caused by process fluctuation. The analog-digital mixing method was used. Combined with adaptive control circuits and high precision hysteresis cA high precision on-chip resistance calibration circuit with the adjustment range of 40 Ω to 100 Ω was designed, which could accurately calibrate the on-chip resistance value caused by process fluctuation. The analog-digital mixing method was used. Combined with adaptive control circuits and high precision hysteresis comparators, the voltage values converted by the on-chip resistance and the referenced off-chip resistance were compared. The circuit was designed to make the on-chip resistance value equal to that of the referenced off-chip. The calibration circuit was designed in a 40 nm CMOS process. The simulation results showed that the minimum voltage comparison threshold of comparator was 2 mV. The circuit could achieve adjustable resistance values in the range of 40 Ω to 100 Ω, and the calibration error was less than 2%..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 336 (2021)
A Reconfigurable Power Divider with Adjustable Phase Difference and Allocation Distribution Ratio
YANG Hong, LEI Peng, PENG Hong, YE Qingsong, and YI Shenghong
A novel power divider with adjustable phase difference and power distribution was proposed on the basis of 3 dB S-parameter characteristics of branch directional coupler. The adjustable function was achieved by changing the length of the two horizontal transmission line. When the sum of the electrical lengths of the twA novel power divider with adjustable phase difference and power distribution was proposed on the basis of 3 dB S-parameter characteristics of branch directional coupler. The adjustable function was achieved by changing the length of the two horizontal transmission line. When the sum of the electrical lengths of the two horizontal transmission lines of the 3dB branch directional coupler was 180°, the adjustable phase shifters based on the varactor diode were used to replace the two 90° horizontal transmission lines, so two continuous and reconfigurable power dividers were designed. By ADS simulation and layout design, the phase difference of the reconfigurable power divider based on the π type phase shifter was adjustable in the range of 244° while those based on the reflective phase shifter was adjustable in the range of 407°, and their distribution ratio were adjustable in the range of -4.6~11.1 dB (about 11 to 101)..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 341 (2021)
Research on Thin-Film HIC Process Based on Gold-Aluminum Bonding Failure
YANG Jiayi, WANG Xuguang, QIN Wenlong, and YANG Liangliang
The failure mechanism of Au/Al bonding in thin film HICs were introduced, a new technique to solve Au/Al bonding failure was proposed. It was found that the Au/Al interface formed by the aluminum wire and the Au guide band of the film was cavitated by atomic diffusion, and the bonding wires at the root of the bond wereThe failure mechanism of Au/Al bonding in thin film HICs were introduced, a new technique to solve Au/Al bonding failure was proposed. It was found that the Au/Al interface formed by the aluminum wire and the Au guide band of the film was cavitated by atomic diffusion, and the bonding wires at the root of the bond were broken. By changing interlaminar structure in the bonding zone, the single metallization system was realized, and the formation of intermetallic compounds was effectively avoided. The results of this study had reference value for broadening the applications of ceramic based thin film HICs..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 347 (2021)
A Novel Security Evaluation Method for Cryptographic Chip
YANG Xue, ZHANG Chi, SHAN Weijun, WANG Lihui, LI Qing, and YU Jun
Security analysis is essential for the cryptographic chip design. The traditional security evaluation methods mainly include leak assessment and side channel attack (SCA), but these need to collect a large number of power traces with much time and professional acquisition equipments. A new idea based on chip simulationSecurity analysis is essential for the cryptographic chip design. The traditional security evaluation methods mainly include leak assessment and side channel attack (SCA), but these need to collect a large number of power traces with much time and professional acquisition equipments. A new idea based on chip simulation waveform for detecting the leakage was proposed in this paper, and a analysis software was designed. The experimental results showed that this novel method could quickly detect the information leakage in the process of encryption or decryption. Besides, there was a qualitative relationship between the number of traces required by the emulational and the actual side channel attack. Compared with the previous technology, it mainly applied to the digital front-end design stage without requirements on hardware devices and could save a lot of time and cost..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 351 (2021)
A Programmable High Speed and Wideband Frequency Divider
LI Jie, XU Hua, WU Yanhui, ZHANG Xiaoyong, ZHANG Zhenrong, LIU Yongguang, and TANG Rui
A programmable high speed and wideband frequency divider was designed and implemented in a 0.18 μm SiGe BiCMOS process. The methods for optimizing high and wideband frequency was analyzed for the divider. A /4/5 or /8/9 prescaler with switchable module value and a M/A counter based on CML difference structure were propA programmable high speed and wideband frequency divider was designed and implemented in a 0.18 μm SiGe BiCMOS process. The methods for optimizing high and wideband frequency was analyzed for the divider. A /4/5 or /8/9 prescaler with switchable module value and a M/A counter based on CML difference structure were proposed, which achieved a wideband working frequency. The measurement results showed that the operating frequency of the divider could cover 1~10 GHz, and the RF input sensitivity of the whole band was lower than -10 dBm..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 357 (2021)
Optimization Design of an ESD Protection Strategy in RF Circuits
PENG Xiong, XU Hua, LIU Tao, CHEN Kun, QIAO Zhe, and YUAN Bo
Three kinds of ESD protection circuits for RF ports were designed in a 0.18 μm SiGe BiCMOS process. The linearity of the RF circuit could be significantly improved through series multistage diodes without affecting the ESD protection capability. Through the series LC resonance network and large inductances in the ESD dThree kinds of ESD protection circuits for RF ports were designed in a 0.18 μm SiGe BiCMOS process. The linearity of the RF circuit could be significantly improved through series multistage diodes without affecting the ESD protection capability. Through the series LC resonance network and large inductances in the ESD diode path, the insertion loss of ESD protection circuit in the RF port could be significantly reduced, and the linearity could also be improved. Simulation results showed that the input 1 dB compression point could be improved to 18.9 dBm through the two-stage series diode structure. At 16 GHz, the series LC resonant network design and the series large inductance design could reduce the insertion loss by 0.5 dB and 0.9 dB, respectively..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 363 (2021)
Optimization Design of a LS-Band VCO Based on Response Surface Modeling
DUAN Wenjuan, LIU Bo, ZHANG Jincan, and MENG Qingduan
A response surface methodology (RSM) based optimization method for improving the performance of a LS-band voltage controlled oscillator (VCO) was proposed. A LC-VCO circuit was designed as an optimization target, and the phase noise and power dissipation were improved by employing cascade cross-coupled transistors as lA response surface methodology (RSM) based optimization method for improving the performance of a LS-band voltage controlled oscillator (VCO) was proposed. A LC-VCO circuit was designed as an optimization target, and the phase noise and power dissipation were improved by employing cascade cross-coupled transistors as load-resistance and an external current mirror bias. Furthermore, the RS model was constructed by fitted data based on circuit simulations, then the best design parameters and the corresponding electric performance could be obtained as the optimal solution. Based on TSMC CMOS 65 nm/1.8 V RF process, the final results showed that all performances of the proposed VCO were improved significantly after optimization. The VCO had a tuning range of 2.377 GHz~2.583 GHz, i.e. 206 MHz, a phase noise of -113.44 dBc/Hz@1 MHZ, and a power consumption lower than 0.66 mW. The FoM value could reach 184.27 dBc/Hz. The proposed LS-band VCO could be applied to the RF transceiver integrated circuits in WiFi, Internet of Things (IoT) and other wireless communications..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 368 (2021)
Review of Error Mitigation Techniques in NAND Flash Memorys
CAO Fuyuan, LIU Yang, and HUO Zongliang
NAND flash memory is widely used for data storage due to its high storage density, high throughput, and low power consumption. The three-dimensional (3D) NAND flash and multi-level cell data coding techniques provide higher density and lower cost per bit, but at the expense of storage reliability. NAND controller compaNAND flash memory is widely used for data storage due to its high storage density, high throughput, and low power consumption. The three-dimensional (3D) NAND flash and multi-level cell data coding techniques provide higher density and lower cost per bit, but at the expense of storage reliability. NAND controller companies have been employing stronger error-correction-codes (ECC) such as BCH and LDPC codes to correct the data errors in NAND flash. But when error number exceeds ECC’s correction capability, the data errors cannot be corrected by ECC. Therefore, several NAND flash error mitigation techniques have been proposed in previous works as supplementary schemes of ECC. In this paper, an introduction of NAND flash memory basics and error patterns was presented, and a review of state-of-the-art error mitigation techniques was given, which provided a useful reference for designing a more reliable storage system..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 374 (2021)
Research Advancement on Interface Passivation of SiC MOSFETs
ZHU Hao, ZHANG Jing, LI Pengfei, and YUAN Shu
The passivation technology of silicon carbide was introduced from five aspects: post-oxidation annealing treatment, nitriding treatment, carbon cap, barium sandwich and post-deposition annealing of oxide. The density of interfacial states could be effectively reduced by improving the passivation process. The influence The passivation technology of silicon carbide was introduced from five aspects: post-oxidation annealing treatment, nitriding treatment, carbon cap, barium sandwich and post-deposition annealing of oxide. The density of interfacial states could be effectively reduced by improving the passivation process. The influence of these passivation processes on the interface state density of SiC/SiO2 was discussed, and the advantages and disadvantages of these passivation processes were analyzed. The passivation methods of annealing and nitriding after oxidation were mainly introduced. Finally, it was found that NO nitrogen technology could effectively reduce the interface density and improve the interface reliability, and it was suitable for manufacturing SiC MOS devices..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 382 (2021)
Research Progress of 1/f Noise Charateristics in Advanced MOSFETs
MA Ting, REN Fang, XIA Shiqin, LIAO Xiyi, and ZHANG Peijian
A comprehensive review of the 1/f noise research progress in advanced Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) was presented. Interfacial states, device structure, material defects, quantum effects and many other factors could affect 1/f noise. With the continuous reduction of process size and the apA comprehensive review of the 1/f noise research progress in advanced Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) was presented. Interfacial states, device structure, material defects, quantum effects and many other factors could affect 1/f noise. With the continuous reduction of process size and the application of high k dielectric, as well as the influence of hot carrier effect, radiation damage and other factors, the origin of 1/f noise in MOSFET had been a huge disagreement and controversy in the academic circle. Only when the real physical origin of 1/f noise was clarified, could it be effectively improved through the process to support the design application..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 390 (2021)
Study on the Effects of Mechanical Stress on β of Bipolar Transistors
LIU Yong, LIU Jian, ZHANG Peijian, WANG Fei, and XIAO Tian
In chip manufacturing process, the mechanical stress has a great influence on common-emitter current gain β of vertical NPN. By slotting on metal 2, the value of β rebounded. A compressive stress layer of Si3N4 was added into the IMD between metal 1 and metal 2, and the β of the largest NPN had returned to normal mode.In chip manufacturing process, the mechanical stress has a great influence on common-emitter current gain β of vertical NPN. By slotting on metal 2, the value of β rebounded. A compressive stress layer of Si3N4 was added into the IMD between metal 1 and metal 2, and the β of the largest NPN had returned to normal mode. At the same time, the β of the other size NPN and PNP still increased. The influence mechanism of stress was analyzed using energy band theory. The results showed that the stress in (100) crystal plane had a great influence on the β of the vertical NPN and vertical PNP, and it had been verified by experiments..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 399 (2021)
An Enhanced HEMT Using P-GaN Gate Combined with Recessed-Gate Technology
QIAO Jie, and FENG Quanyuan
In order to obtain a high breakdown voltage and high threshold voltage enhancement-mode GaN device, a P-doped GaN (P-GaN) gate combined with recessed-gate AlGaN/GaN/AlGaN double heterojunction device was proposed. The threshold voltage of the device was up to 3.4 V, and the breakdown voltage was up to 738 V. Using SentIn order to obtain a high breakdown voltage and high threshold voltage enhancement-mode GaN device, a P-doped GaN (P-GaN) gate combined with recessed-gate AlGaN/GaN/AlGaN double heterojunction device was proposed. The threshold voltage of the device was up to 3.4 V, and the breakdown voltage was up to 738 V. Using Sentaurus TCAD for simulation, the threshold voltage and breakdown voltage of the traditional P-GaN gate and the P-GaN gate with recessed-gate AlGaN/GaN/AlGaN double heletrojunction device were compared. The results showed that, when the recessed-gate depth was changing at 5~13 nm, the threshold voltage increased with the recessed-gate depth, and the breakdown voltage first increased and then decreased slightly with the recessed-gate depth. The on resistance increased with the recessed-gate depth, and the minimum on resistance was 11.3 Ω·mm..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 404 (2021)
An Improved Fast Turn-on Low-Trigger DTSCR
JIANG Guijun, DU Feibo, LIU Jizhi, and LIU Zhiwei
A fast turn-on low-trigger improved DTSCR (MDTSCR) was proposed. Based on the traditional DTSCR, the MDTSCR added a current gain amplifier module, which greatly had improved the current gain of the parasitic bipolar junction transistor, reduced the trigger voltage, and improved the opening speed of the device. The expeA fast turn-on low-trigger improved DTSCR (MDTSCR) was proposed. Based on the traditional DTSCR, the MDTSCR added a current gain amplifier module, which greatly had improved the current gain of the parasitic bipolar junction transistor, reduced the trigger voltage, and improved the opening speed of the device. The experimental results showed that, compared with traditional DTSCRs, the turn-on time of the MDTSCR was reduced by 52%, and the trigger voltage was decreased from 5.5 V to 4.5 V under a 28 nm CMOS process. The MDTSCR achieved a best protection performance by adjusting the number of diodes to adapt to the different design windows at 28 nm CMOS process..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 409 (2021)
TCAD Simulation of Si/Ge Heterojunction Double-Gate Tunneling FET
WANG Hanbin, LIU Mengxin, BI Jinshun, and LI Wei
Compared to the conventional silicon-based Double Gate Tunneling Field Effect Transistor (DGTFET), the Si/Ge heterojunction DGTFET shows better electrical performance. Based on Sentaurus TCAD, two types of Si/Ge heterojunction DGTFET with/without pocket structure had been established. The performance of the device was Compared to the conventional silicon-based Double Gate Tunneling Field Effect Transistor (DGTFET), the Si/Ge heterojunction DGTFET shows better electrical performance. Based on Sentaurus TCAD, two types of Si/Ge heterojunction DGTFET with/without pocket structure had been established. The performance of the device was studied by insight into the effects of pocket structure, thickness and doping concentration of the pocket region on the on-state current (Ion), off-state current (Ioff), subthreshold swing (SS), cut-off frequency(fT) and gain bandwidth product (GBW). Through simulation experiments and calculation analysis, it was found that the Ion, Ioff, SS, fT and GBW of Si/Ge heterojunction DGTFET increased with the increase of doping concentration in the pocket region. The thickness of the pocket region had no obvious effect on the device performance. The results of the study provided a good guidance for the optimization of DC and frequency characteristics of the TFET device..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 413 (2021)
Research on MEMS Microwave Power Sensor with Symmetric Double Cantilever Beams
ZUO Wen, LIU Qicai, ZHANG Congchun, and WANG Debo
In order to improve the measurement sensitivity of capacitive MEMS microwave power sensors, the internal space of the sensor was fully utilized, and a novel capacitive microwave power sensor based on symmetric double cantilever beams was proposed in this paper. Based on the structure of symmetric double cantilever beamIn order to improve the measurement sensitivity of capacitive MEMS microwave power sensors, the internal space of the sensor was fully utilized, and a novel capacitive microwave power sensor based on symmetric double cantilever beams was proposed in this paper. Based on the structure of symmetric double cantilever beams, a pivoted electro-mechanical model was established, and the measurement sensitivity and overload power of the sensor were researched and analyzed. The results showed that the sensitivity of symmetric double-beam structure was three times higher than that of traditional single-beam structure with the same initial gap of the cantilever beam. Meanwhile, a wide-range tradeoff between sensor’s sensitivity and overload power could be realized by changing the initial gap of the cantilever beam. Therefore, the proposed symmetric double-beam structure could meet design demand widely..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 418 (2021)
Analysis of Factors Affecting the Flatness of On-Resistance for 30 V UMOS
ZHOU Xi, and FENG Quanyuan
The flatness of on-resistance is an important performance of the power device when it is used as a switching device. The factors which have considerable influences on the flatness of on-resistance have been studied and optimized to improve the performances of the device. The specific channel resistance is a major part The flatness of on-resistance is an important performance of the power device when it is used as a switching device. The factors which have considerable influences on the flatness of on-resistance have been studied and optimized to improve the performances of the device. The specific channel resistance is a major part of on-resistance for the UMOS with a low breakdown voltage. Therefore, the computed equation of the channel resistance was given and analyzed in this paper. The trends of the on-resistance flatness were investigated with the P-base implant dose and the gate oxide thickness using Sentaurus TCAD simulation. The simulation results showed that a better flatness of on-resistance could be obtained by reducing the gate oxide thickness and the implant dose of P-base region..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 424 (2021)
Analysis of Geometric Effect on 8-Shape NMOS Under TID
WU Yucao, LUO Ping, and JIANG Pengkai
The study of geometric effect on the electric property damage and degradation of 8-shape NMOS under TID (Total Ionizing Dose) radiation, and the comparison of immunity to which between standard and 8-shape NMOS with parameter variation differences were presented. As results showed, compared with standard NMOS, the inflThe study of geometric effect on the electric property damage and degradation of 8-shape NMOS under TID (Total Ionizing Dose) radiation, and the comparison of immunity to which between standard and 8-shape NMOS with parameter variation differences were presented. As results showed, compared with standard NMOS, the influence of gate-active region overlaid width and aspect ratio on the 8-shape NMOS off-state current could be ignored. Drain saturation current of 8-shape NMOS with any geometric change, compared with standard NMOS, showed a better ability to be stable, regardless of TID levels. Meanwhile, differences of drain saturation current under small aspect ratio circumstance came from the variation of gate-active region overlaid width, which no longer existed as a contributor to the drain saturation current differences of 8-shape NMOS with big aspect ratio. Threshold voltage of all tested 8-shape NMOS fabricated in 180 nm process stayed at 0.41 V stably, superior to standard NMOS..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 429 (2021)
A GaN-Based High Voltage Schottky Barrier Diode with Double Heterojunction
HAN Chunlin, SUN Tao, and ZHOU Jianjun
A novel high voltage and low power Schottky barrier diode (SBD) with double-heterojunction was theoretically and experimentally investigated on the GaN/AlGaN/GaN/Si substrate. Owing to the polarization effect, the two-dimensional hole gas (2DHG) and electron gas (2DEG) were formed at the GaN-top/AlGaN and AlGaN/GaN intA novel high voltage and low power Schottky barrier diode (SBD) with double-heterojunction was theoretically and experimentally investigated on the GaN/AlGaN/GaN/Si substrate. Owing to the polarization effect, the two-dimensional hole gas (2DHG) and electron gas (2DEG) were formed at the GaN-top/AlGaN and AlGaN/GaN interface, respectively. Firstly, with the increase of bias voltage, the 2DHG and 2DEG gas were completely exhausted, leaving a fixed positive/negative polarization charge at the interface to form a polarization junction. The power lines shifted from positive charge to negative charge, which made the distribution of the electric field in the drift area more uniform, and improved the breakdown voltage of the diode. Secondly, the GaN/AlGaN layer of the Schottky diode was completely etched to obtain a low turn-on voltage. Finally, a low damage ICP etching process was developed to reduce the defects of the Schottky contact interface, and to reduce the reverse leakage current and turn-on voltage. The experimental results showed that the breakdown voltage of the diode was 1 109 V@1 mA/mm, the turn-on voltage was 0.68 V, the specific on-resistance was 1.17 mΩ·cm2, and the Baliga FOM value was 1 051 MW/cm2. The SBD had the characteristics of high breakdown voltage, low turn-on voltage and good uniformity.
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 439 (2021)
Total Ionizing Dose Effect of Enhancement-Mode GaN Power Devices
CHEN Siyuan, YU Xin, LU Wu, WANG Xin, LI Xiaolong, LIU Mohan, SUN Jing, and GUO Qi
High and low dose-rate radiation damage effects of P-type cap and cascode structure gallium nitride power devices were investigated. Experimental results showed that neither P-type cap nor cascode structure gallium nitride power device had Enhanced Low Dose Rate Sensitivity effect (ELDRS). The electrical parameters of High and low dose-rate radiation damage effects of P-type cap and cascode structure gallium nitride power devices were investigated. Experimental results showed that neither P-type cap nor cascode structure gallium nitride power device had Enhanced Low Dose Rate Sensitivity effect (ELDRS). The electrical parameters of cascode structure gallium nitride power devices degraded more obviously after total ionizing dose irradiation. The P-type cap structure of GaN power devices had strong resistance to total ionizing dose. The mechanism of the degradation in electrical parameters after irradiation was analyzed. The experimental results of this study provided a useful reference for comprehensively evaluating GaN power devices utilized for space applications..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 444 (2021)
Optimization Research of Automatic Eutectic Die Attach Parameters for Au80Sn20 Alloy
LI Maosong, HUANG Dazhi, ZHU Hongjiao, and HU Qiong
An orthogonal experimental method was used to optimize the parameters of automatic eutectic die attach for controlling the void rate and shear strength. The three key parameters of attach temperature, attach time and attach pressure were analyzed by three factors and two levels of orthogonal method. The primary and secAn orthogonal experimental method was used to optimize the parameters of automatic eutectic die attach for controlling the void rate and shear strength. The three key parameters of attach temperature, attach time and attach pressure were analyzed by three factors and two levels of orthogonal method. The primary and secondary factors which were affecting eutectic attach quality was obtained, and the best optimal combination of attach parameters was also obtained. The experimental results showed that the die eutectic attach quality was improved obviously by using the optimized parameters combination. The average void rate of die eutectic soldering zone and the Cpk value of chip shear force were fully meeting the requirements of GJB548B..
Microelectronics
- Publication Date: Jan. 01, 1900
- Vol. 51, Issue 3, 449 (2021)
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