• Microelectronics
  • Vol. 51, Issue 2, 168 (2021)
GUO Liang, ZENG Tao, HUANG Feilin, LEI Langcheng, SU Chen, LIU Fan, and LIU Luncai
Author Affiliations
  • [in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.200293 Cite this Article
    GUO Liang, ZENG Tao, HUANG Feilin, LEI Langcheng, SU Chen, LIU Fan, LIU Luncai. A High Speed Sample and Hold Circuit Using Low Threshold Technology[J]. Microelectronics, 2021, 51(2): 168 Copy Citation Text show less
    References

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    [2] ALI A M A, DINC H, BHORASKAR P, et al. A 14-bit 2.5 GS/s and 5 GS/s RF sampling ADC with background calibration and dither [C] ∥ VLSI-Circuits. Honolulu, HI, USA. 2016: 1-2.

    [3] SEHGAL R, FRANK V D G, BULT K. A 13-mW 64-dB SNDR 280-MS/s pipelined ADC using linearized integrating amplifiers [J]. IEEE J Sol Sta Circ, 2018, 53(7): 1878-1888.

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    [7] ALI A M A, DINC H, BHORASKAR P, et al. A 14-bit 1 GS/s RF sampling pipelined ADC with background calibration [J]. IEEE J Sol Sta Circ, 2014, 49(12) :2857- 2867.

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    GUO Liang, ZENG Tao, HUANG Feilin, LEI Langcheng, SU Chen, LIU Fan, LIU Luncai. A High Speed Sample and Hold Circuit Using Low Threshold Technology[J]. Microelectronics, 2021, 51(2): 168
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