Fig. 1. (Color online) (a) Comparison between conventional and SC methods, SNs length =N bits. (b) Region of the image. (c) The stochastic computational element to realize image detection algorithmic in logic circuits. (d) Scaled addition realized by the OR gate, scaled subtraction, and absolute value calculation realized by the XOR gate. (e) The data processing flow chart in the proposed method.

Fig. 2. (Color online) (a) The NOR flash architecture for logic operation. (b)I–V curve for NOR flash array. (c) Memory window degradation by P/E cycling. (d) Read current fluctuations can be observed caused by RTN.

Fig. 3. (Color online) (a) BER comparison between the conventional method and SC method when the signal noise is considered. (b) Effects of simultaneous offset of device parametersV_G/V_D/V_th on BER. (c) RTN effects are ignorable on BER. (d) Add 10% noise in (b). (e) Under differentV_G/V_D conditions, effects of simultaneous 10% drift of three device parameters on BER(N = 2). (f) Effects ofV_th shifts.

Fig. 4. (Color online) (a) BER and (b) power consumption at variousV_G/V_D voltages whenN = 2.

Table 0. XOR truth table (V_D = 1 V).

Table 0. OR truth table (V_G = 3 V,V_D = 1 V).