• Microelectronics
  • Vol. 51, Issue 3, 413 (2021)
WANG Hanbin1、2, LIU Mengxin1, BI Jinshun1、3, and LI Wei2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.200340 Cite this Article
    WANG Hanbin, LIU Mengxin, BI Jinshun, LI Wei. TCAD Simulation of Si/Ge Heterojunction Double-Gate Tunneling FET[J]. Microelectronics, 2021, 51(3): 413 Copy Citation Text show less
    References

    [1] CHOI W Y, PARK B G, LEE J D, et al. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J]. IEEE Elec Dev Lett, 2007, 28(8): 743-745.

    [2] ASTHANA P K, GHOSH B, GOSWAMI Y, et al. High-speed and low-power ultradeep-submicrometer III-V heterojunctionless tunnel field-effect transistor [J]. IEEE Trans Elec Dev, 2014, 61(2): 479-486.

    [3] ZENER C. A theory of the electrical breakdown of solid dielectrics [J]. Proceed Royal Soc A, 1934, 145(855): 523-529.

    [4] STUETZER O M. Junction fieldistors [J]. Proceed IRE, 1952, 40(11): 1377-1381.

    [5] QUINN J J, KAWAMOTO G, MCCOMBE B D. Subband spectroscopy by surface channel tunneling [J]. Surface Sci, 1978, 73: 190-196.

    [6] SINGH G, AMIN S I, ANAND S, et al. Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation [J]. Superlatt & Microstruct, 2016, 92: 143-156.

    [7] BOUCART K, IONESCU A M. Double gate tunnel FET with ultrathin silicon body and high-k gate dielectric [C] // Europ Sol Sta Dev Res Conf. Montreux, Switzerland. 2006: 383-386.

    [8] SHIH P C, HOU W C, LI J Y. A U-gate InGaAs/GaAsSb heterojunction TFET of tunneling normal to the gate with separate control over on-and off-state current [J]. IEEE Elec Dev Lett, 2017, 38(12): 1751-1754.

    [9] MAMILLA B K, MISHRA R, NAIR S, et al. A III-V group tunnel FETs with good switching characteristics and their circuit performance [J]. Int J Elec Commun & Compu Technol, 2011, 1(2): 26-29.

    [10] CHANDAN B V, NIGAM K, PANDEY S, et al. Temperature sensitivity analysis on analog/RF and linearity metrics of electrically doped tunnel FET [C] // CICT. Gwalior, India. 2017: 1-5.

    [11] HU C, CHOU D, PATEL P, et al. Green transistor -a VDD scaling path for future low power ICs [C] // Int Symp VLSI-TSA. Hsinchu, China. 2008: 14-15.

    [12] SHIH C H, CHIEN N D. Sub-10-nm tunnel field-effect transistor with graded Si/Ge heterojunction [J]. IEEE Elec Dev Lett, 2011, 32(11): 1498-1500.

    [13] SHIH C H, CHIEN N D. Physical operation and device design of short-channel tunnel field-effect transistors with graded silicon-germanium heterojunctions [J]. J Appl Phys, 2013, 113(13): 2281-2283.

    WANG Hanbin, LIU Mengxin, BI Jinshun, LI Wei. TCAD Simulation of Si/Ge Heterojunction Double-Gate Tunneling FET[J]. Microelectronics, 2021, 51(3): 413
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