Magnetic random access memory (MRAM), as an emerging non-volatile memory, features high read and write speed, high endurance, long storage time and low-power dissipation, and has captured considerable interest in large semiconductor foundries, such as TSMC, Samsung and GlobalFoundries a few years ago^[1-5]. On the one hand, MRAM’s high performance characteristics help it to become an important solution to replace the embedded flash (e-flash) memory below 28 nm CMOS technology node, whereas e-flash has severe economic barriers that hampers its further scaling^[6]. On the other hand, MRAM is aimed as an alternative to become working memories, such as static random-access memory (SRAM) to solve severe potential leakage in the advanced CMOS node^[7,8]. However, it is difficult to replace L1 or L2 cache SRAM due to the speed limitations and endurance problems, especially for two-terminal spin-transfer torque (STT) MRAMs^[9-11]. Thus, the further exploration of next-generation MRAM devices is needed.

Based on the writing mode^[12], MRAMs can be classified into three main categories: toggle MRAM, STT MRAM and spin-orbit torque (SOT) MRAM. Toggle MRAM is the first generation of commercial MRAM, which utilize the Oster field generated by the current to reverse the free layer magnetization^[13]. However, difficulties such as, scaling-down and high-power consumption limit its development. Two-terminal STT MRAM devices use the current-induced spin-transfer torque to switch the free layer magnetization^[14-17]. The high write current density stresses the tunnel barrier during the write operation, then degrades its reliability^[18-21]. To solve the reliability issues of the STT MRAM, SOT MRAM is proposed because read and write paths are separated in three-terminal devices which intrinsically solves the read error issue and tunnel barrier aging issues due to high write current^[22-26].

Nevertheless, SOT MRAM is still in the research and development phase because there are several challenges in the wafer-level manufacturing process. These challenges stem mainly from two aspects. First, the commercialized STT MRAM usually consists of bottom-pinned perpendicular magnetic tunnel junctions (p-MTJ) stack structure. For this kind of film stack, the free layer is on the top of the structure, which is not sensitive to the roughness of the substrate because of the thicker bottom seed layer and synthetic antiferromagnetism (SAF)/reference layer (RL). Unlike STT MRAM, SOT MRAM currently uses a top-pinned film structure. The heavy metal and free layer are adjacent to the substrate, and the substrate roughness plays a key role in the film quality of the upper film, thus affecting the electrical and magnetics performance of the MTJs. Therefore, it is challenging to integrate MTJ in commonly used back-end-of-line (BEOL) process because of the severe influence of the surface roughness on MTJ film performance^[27]. Second, the SOT channel is ultra-thin to obtain as large as possible charge-to-spin conversion efficiency due to relatively small spin diffusion length. This ultra-thin SOT channel would give more challenges on how to etch stop exactly on the channels across the wafer. This issue needs to be solved for wafer level manufacturing^[28]. In view of these challenges, several research groups have focused their efforts on developing wafer-level SOT MRAM devices. For example, Singapore IME successfully prepared a 200-mm-wafer-level in-plane SOT MTJs using thick Pt as a heavy metal (HM) layer. The tunnel magnetoresistance ratios (TMR) of these devices are 80%–100%^[29]. However, the prepared device was not integrated by the BEOL process. Moreover, the resistance of SOT track is too large, which cannot match with the CMOS integrations. In 2019, Tohoku University demonstrated the canted field-free SOT MRAM with excellent device performance on 300 mm wafer. They systematically tested various parameters of the devices and showed that the in-plane SOT MRAM has a favorable development prospect. However, the data they presented are based on the performance of single devices, there is no description about the wafer-level uniformity^[26]. Taiwan’s Industrial Research Institute also designed an 8 kb in-plane SOT MRAM chip based on 200 mm wafer for the first time. However, the most important endurance results are not clarified clearly and there are no data shown to support the uniformity performance at wafer level^[30].

In view of these problems, the purpose of our present study is to demonstrate the manufacturing capability of wafer-level SOT MTJ devices. We integrated in-plane SOT MTJ devices by the 200-mm-wafer platform, using a two-metal-layers BEOL process. Film structural information, electrical properties, and reliability performance are systematically studied for the SOT devices that we have fabricated.

SOT MTJs were integrated by the 200-mm-wafer manufacturing platform.Figs. 1(a) and1(b) show the three-dimensional schematic pictures of the MTJ device and the corresponding cross-section transmission electron microscopy (TEM) image cutting along the SOT track (x-direction), respectively. The substrate, consisting of one metal layer and one via, was prepared by the foundry through the so called “short loop” process flow. The process and design rules of the metal line and the via are the same as that of “Metal5” and “Via5” widely used in the common 0.18μm CMOS technology node. As can be seen inFigs. 1(a) and1(b), the isolated SOT MTJs are designed using Kelvin structure located between the vias and on top of the dielectric materials. Following the arrow sequence, the SOT MTJs process cartoon flow is illustrated inFigs. 1(c)–1(f). The substrate was first treated under a chemical mechanical polishing process to obtain sufficiently low roughness (< 0.2 nm) required for MTJ stacks^[26]. The bottom image ofFig. 1(c) is scanned by atomic force microscope (AFM) in the SOT MTJ area. TheR_a value in the marked white box area is 0.155 nm, which is perfect for the following MTJ stack deposition. Second, the SOT track and the MTJ stack were deposited in a 200 mm capable PVD tool with thickness nonuniformity of 1.6% across the wafer confirmed through the 49 points resistivity measurements. The stacks featuring in-plane magnetic anisotropy are composed of (from the bottom to the top) W (5)/CoFeB (1.3)/MgO (1.5)/CoFeB (1.9)/CoFe (0.8)/Ru (0.8)/CoFe (2.5)/IrMn (7.5)/Ta (3)/Ru (2)/Ta (2). The numbers in parentheses signify every layer thickness in nanometers. Here, we use W as the SOT HM layer. As well known, W has a relatively large charge-to-spin conversion efficiency, i.e., spin Hall angle (SHA) ~ –0.3 for theβ-W phase^[31]. The first CoFeB next to W is the free layer (FL), the magnetization direction of which can be switched effectively due to the spin current generated by the spin-Hall effect (SHE) or/and Rashba effects at the interface of HM/FL once the current pass through the SOT HM layer. The CoFeB/CoFe/Ru/CoFe/IrMn multilayers are used as a synthetic antiferromagnetic (SAF) layer for pinning the second CoFeB reference layer, which can also effectively reduce the stray field. Top Ta/Ru/Ta layers are used as a protective cap and top electrode, which can simultaneously avoid oxidation. The MTJ resistance area products (RA) are 4863 Ω·μm² obtained by the CIPT method, with 7.2% nonuniformity across the wafer. The whole wafer was subsequently annealed at 300 °C under a magnetic field of 1 T. Next, the SOT MTJs were patterned through i-line photolithograph and combination of reactive ion etching (RIE) and ion beam etching (IBE). The optimized IBE can stop the etching exactly on the SOT track determined by signals of the second ion mass spectrometer. 700 × 2100 nm² MTJs are successfully patterned with just etch stop at the SOT track layer surface, non-residual at the side wall of the MTJ, and low damage at the same time (Fig. 1(b)). In subsequent devices tests, the open rate and short rate of the full wafer are less than 5%. The baseline devices are designed as so-called “Type-Y” MTJs^[25] with an ellipse of a short axisa = 700 nm along the SOT track direction, i.e.,x-axis. The long axis has a width with a 3 : 1 aspect ratio to the short axis, i.e.,b = 2100 nm, pointing to the direction perpendicular to the SOT track (y-axis). Meanwhile, few other MTJs with smaller critical dimensions (CD), such asa = 300 nm and 500 nm, are also patterned with various aspect ratios for the size dependence study purpose. Afterin-situ encapsulations, the SOT track is patterned to a dumbbell shape having 2500 nm width as shown in the bottom ofFig. 1(e). The width of the SOT track is larger than that of the MTJ long axis widthb and has enough overlay margins that take account of our process limitations. Finally, top electrodes are fabricated using a common Al pad process. After fabrications, the electrical tests, e.g.,R–H,R–V and so on were carried out. These tests allow us to systematically investigate the performance of devices, which include short pulse width switching probability, reliability performance, such as endurances, and data retentions. TheR–H loop was performed by applying an in-plane magnetic field of –100 – +100 Oe along the long axis while the MTJ junction resistance was read. TheR–V loop was tested using a 200-mm probe station with Keysight 2912b to read the MTJ junction resistance while applying a –2 – +2 V voltage to the SOT channel. Keithley 4200 was used to provide the short pulse for switching probability and endurance measurements. We defined the TMR ratio as (R_AP –R_P)/R_P, whereR_AP andR_P are the resistances for the antiparallel and parallel magnetization configurations between the free layer and the reference layer.

We first describe the structural properties of the prepared SOT MTJs. Detailed structural information of the MTJ film stack was analyzed by the TEM. The high-resolution TEM (HRTEM) images are shown inFig. 2(a) which are captured from theFig. 1(b) sample. The images show flat and clear interfaces between W/CoFeB/MgO/CoFeB layers. Simultaneously with the HRTEM, energy dispersive X-ray spectroscopy (EDS) mapping analysis was performed for the same sample.Figs. 2(c)–2(f) are the corresponding EDS mappings of each element; that is, W, Mg, Co, and Fe, respectively. These images suggest that each layer is uniformly deposited, indicating no clear interdiffusion at the 300 °C annealing temperature. We also performed nano-beam diffraction analysis through fast Fourier transforms (FFT) from HRTEM images to further characterize the film quality, especially focused on the W layer.Fig. 2(b) is the FFT analysis image of the W layer from the selected red box region inFig. 2(a). As can be seen,Fig. 2(b) shows a vague halo combining with a few weak diffraction spots, which suggests our 5 nm W is a more amorphous-like film with some lattice fringes coexisting. The spots likely correspond toα-W {110}^[32]. However, it is hard to distinguish between theα-W {110} and theβ-W {210} since the inter-planes’ distances are close to each other. From the FFT results, we could not identify the presence of theβ-W. The simplified film structure, which is the bottom part of the SOT MTJ stacks and consisting of W/CoFe/MgO/Ta, was carried out for the X-Ray Diffraction (XRD) measurements. FromFig. 2(g), the XRD clearly showsβ-W {200} and {211} peaks besidesβ-W {210} and/orα-W {110} peaks. The resistivities of W with various thicknesses (Fig. 2(h)) were also measured in this kind of short stack structure. The resistivity of 5 nm W is around 100 μΩ∙cm, which is just at the median point between theβ-W andα-W resistivities. This resistivity result indicates that our prepared 5 nm W is at theβ to α phase transition boundary and it is consistent with the observations from the previously discussed structural properties analysis. In conclusion, we observed the co-existence ofα-W,β-W and amorphous W for our 5 nm W SOT track that may provide reasonable SHA.

Furthermore, we describe the electrical characteristics of the fabricated SOT MTJs across the 200-mm-wafer throughR–H andR–V measurements at room temperatures.Fig. 3(a) shows typicalR–H hysteresis loops of the SOT MTJs. The magnetic fields were applied along the in-plane magnetic easy axis during theR–H measurements. The SOT MTJs show a high TMR ratio of 102% as seen inFig. 3(a), which is close to that of 114% obtained from the CIPT measurements at the film stack level. This result indicates a low damage during the MTJ fabrication process and low series resistances.Fig. 3(b) shows the correspondingR–J curves obtained from the same junction inFig. 3(a). The TMR ratio of 107% obtained from theR–V curves is comparable to that of the value from theR–H curves. The switching current density is –25 MA/cm² for P to AP direction and +29 MA/cm² for the AP to P direction. The unbalanced switching current density in two directions is probably due to the non-zero magnetic stray field from the SAF layers. The average current density of 20 MA/cm² is comparable to the commercialized STT MRAM^[33]. However, with smaller channel resistances than those of STT MTJ, our results indicate a possibly lower write power consumptions in SOT MTJ devices.

Next, the wafer-level distributions of the previously-mentioned electrical parameters were examined.Figs. 3(c)–3(e) show the distributions of electrical parameters such asR_SOT, TMR ratio, and theJ_SW (switching current densities) of over 286 measured normal SOT MTJs across the 200-mm wafer. As references, the box plots are also shown on the right-hand side of the distribution pictures.Figs. 3(f)–3(h) are corresponding cumulative distribution function (CDF) plots as an alternative view of the distributions besides the box plots. As can be seen,R_SOT is screwed to one side with a median value of 650 Ω, matching with the designed resistance value. The out-screwed data (sigma% = 18%), especially on higher resistance side, probably happens because of the etch depth non-uniformity due to the ultra-thin W layer we used. Nevertheless, the range and sigma of theR_SOT are still acceptable, well within the CMOS transistor driving capability (this will not be discussed here as it is beyond the scope of this paper). Meanwhile, TMR ratios andJ_SW both follow the normal distributions, with sigma% of 7% and 20%, respectively. The relatively high sigma% ofJ_SW is probably linked to the non-uniformity ofR_SOT that we observed. To improveR_SOT and associatedJ_SW, uniformity robust etch process and thicker SOT track materials might be necessary.Fig. 3(i) shows the bit-cell resistance distributions of 286 SOT MTJs for both P and AP states. A wide separation betweenR_P andR_AP, about ~5R_P sigma, indicates that there is enough read margin to use differential sensing^[34] or self-reference sensing methods^[35]. This might provide a possibility for utilization of the middle point sensing method^[36] but some efforts still needed for the process integration improvement. Overall, wafer level electrical characterizations suggest a relatively good uniform process capability of our 200-mm SOT MRAM manufacturing platform.

The CD dependence of the switching current in our SOT MTJs was also investigated.R–V measurements were carried out for the SOT MTJs with various short axisa and long axisb. It should be noted that the width of the bottom electrode is the same for different MTJ CDs.Fig. 4(a) shows the normalized switching current as a function of long axisb. TheI_SW is normalized by the average value of the current for MTJs with baseline sizeb = 2100 nm. Surprisingly, the current decreases strongly and monotonically with the scaling of the MTJ long axisb. TheI_SW of MTJs withb = 500 nm is almost 50% of that baseline MTJ withb = 2100 nm. Even though the current drop is suitable for CMOS integration, this behavior is still different from the well-known SOT critical switching current equation, as follows^[37]:

ISW=2eℏαμMStFLξ(Hani+Heff)wd,

because there are no MTJ CD related parameters can be found in the equation.

In Eq. (1),e is the electron charge, ℏ is the reduced Planck constant, α is the damping constant,μ is the permeability of vacuum,M_S is the saturation magnetization,t_FL is the free layer thickness,ξ is the spin polarization of spin current,H_ani is the magnetic shape anisotropy field,H_eff is related to the demagnetization field,w andd are the SOT HM channel width and thickness, respectively.

We note that the equation is an ideal case, which does not consider the current shunting effect. Severe current shunting would have happened in SOT MTJ devices when the current is applied on the SOT track because the free layer resistance, i.e., CoFeB, is lower than that of SOT HM, i.e., W in our case. We then use a simplified parallel circuit model^[38] to extract the current passing through the W contributing to the switching and another portion of current passing through the free layer, accordingly.

ISW=ISOT+IFL,

ISOT/IFL=ρCFBwd/ρWbt,

wherew is the SOT channel width 2500 nm,d is the SOT W channel thickness 5 nm,b is the MTJ long axis varied from 500 to 2100 nm,t is the free layer thickness 1.3 nm,ρ_CFB is the resistivity of free layer 127μΩ∙cm, andρ_W is the resistivity of W 90μΩ∙cm. After calculations, the normalizedI_FL andI_SOT are illustrated inFigs. 4(b) and4(c). It is clear that the normalizedI_FL declines 80% from the baseline values. However,I_SOT shows only a minor change of ~10%, suggesting that charge-to-spin conversion efficiencies are similar with different CDs and the equation (1) is still valid when CD changes. We also checked the ratios ofI_FL/I_SW as shown inFig. 4(d), which follows the trends of CD dependence ofI_FL as theI_FL reduction plays a dominant role in the results ofFigs. 4(b) and4(c). Based on the results, the CD dependence ofI_SW could be explained by minimizing the current shunting effect as CD shrinks. Therefore, beyond enhancing charge-to-spin conversion efficiency, eliminating the current shunting effect would be important for the switching current reduction of SOT MTJ devices to match with the CMOS scaling.

The switching current for the SOT MTJ devices was further investigated with various pulse widths (from 100 ns to 50μs) applied on the W track.Figs. 5(a) and5(b) show the switching probability (P_SW) as a function of applied voltage when pulse widths were varied from 50μs down to 100 ns for both P-to-AP and AP-to-P directions. As can be seen, theP_SW changes sharply from 0 to 1 with only about 10% of switching current densities increasing, indicating a reliable switching occurred for our SOT MTJ devices. We also note that the current densities obviously increase with the decreasing of pulse widths, which is like the STT switching behavior^[39]. Similarly, we evaluated the dependence of the switching current on the pulse widths.Fig. 5(c) shows switching current density atP_sw = 50% of various pulse widths for both P-to-AP and AP-to-P directions, extracted fromFigs. 5(a) and5(b). At 100 ns pulse width, the switching current density is around –37 MA/cm² for AP-to-P and +44 MA/cm² for P-to-AP, respectively. The values are twice as compared with the DC measurement described before. The switching write current density of SOT MTJ can be expressed as^[40]

JC=JC0[1−1Δln(tt0)],

whereJ_C0 is the zero-thermal critical switching current,Δ is the thermal stability factor (Δ =E_b/k_BT),E_b is the energy barrier, andt₀ is the initial time for thermally-activated switching, normally 1 ns. FromFig. 5(c), we extract theJ_C0 is around ±38.6 MA/cm² by fitting the data using Eq. (4). Despite the large size of the MTJ in our work, the estimatedJ_C0 is smaller than that reported in Ref. [41]. Based on the data, our SOT MTJ devices are capable of low power consumption and could match the conventional CMOS operating voltages.

Let us now describe the reliability properties of fabricated SOT MTJ devices. First, we checked the endurance performance, which is theoretically one of the merit points compared with STT MTJ devices^[42]. The endurance test was carried out on the device-level by applying current pulse cycles with 200 ns width and constant 58 MA/cm² current density. The current density used in the endurance test is 1.5 times large ofJ_SW, taking into account of the wafer-level variations.Fig. 6(a) showsR_SOT,R_P, andR_AP measured after the corresponding cycling current pulses for a typical SOT MTJ device. As illustrated, there were no apparent changes ofR_SOT,R_P, andR_AP during the test, even after 10¹⁰ write cycles. The test was stopped just after 10¹⁰ cycles because of time limitations. Even though we only have data at 10¹⁰ cycles level, it would be better than those of commercialized embedded STT MRAM devices^[43] and would be possible to achieve higher cycles as claimed by the first-generation field-driven toggle MRAM^[13]. We also note that theR_SOT of W channel remains nearly the same, which satisfies the electromigration (EM) requirement even if it is not a stringent EM qualification method^[44]. During the endurance test, the MR loops were recorded multiple times at each power of 10 pulses up to 10¹⁰ (Fig. 6(b)). The normalR–V tests were also measured at the same time besides theR–H tests (Fig. 6(c)). As can be seen, the variations in the TMR ratios and the switching current density of the tested device are less than 1%, respectively. These results show the outstanding endurance and high-reliability of our fabricated SOT MTJ devices.

The data retention performance, which is another reliability metric of the non-volatile memory^[45], was also examined. The thermal stability factor (Δ) is the critical parameter that determining data retention. To evaluateΔ, we conducted two kinds of data retention tests, one for the device-level and another for the chip-level. For the device-level measurements,R–H loops were measured for the same device by 500 times. Then,H_C dependence of switching probabilities is extracted from theR–H loops. Finally,Δ could be fitted by the following equation^[46]:

PSW=1−exp{−ττ0exp[−Δ(1−H−HSHkeff)2]},

whereτ andτ₀ are the relaxation time and attempt time, typically 1 ns.H is the external magnetic field,H_S is the coupling field due to the magnetic stray field, and Hkeff is the anisotropy field.Fig. 7(a) shows the extracted switching probabilities as a function of the external magnetic field and the corresponding fitting curve in red. The fittingΔ is around 100k_BT, which is large enough for Gb-size memory array maintaining the data over 10 years. We also checked theΔ for the MTJs with various CDs which are described before based on 7 devices for every CD by the same method as shown inFig. 7(b). The diamond plots ofΔ are comparable for the MTJs even ifb scales down to 1000 nm. This probably happens because our MTJs’ CD is still large. However, please note that Eq. (5) is assumed to be valid for the single magnetic domain^[47]. Then, the fittedΔ would be overestimated as our junction size is much larger than the typical single domain (<100 nm). To accurately obtain theΔ values, the chip-level retention test was conducted generally using the thermal acceleration test, which has been preferred in the industry. We estimate 200-mm-wafer level data retention performance by checking the failure-bit rate of the array through baking the wafer at 200 °C with several baking time.Fig. 7(c) shows the failure-bit rates of different bake time; that is, 12, 24, and 48 h at 200 °C, respectively. We then, used the Eq. (6) as follows to fit the chip-levelΔ^[48]:

ln(F)=ln(t)+ln(F0)−(Δ−Δsigma22),

whereF is the failure-bit rate,t is the bake time,Δ_sigma is the deviation ofΔ. Here, we roughly use 10% to estimate theΔ_sigma% for the fitting, which is from the wafer-levelR_P distribution mentioned earlier. The transmitted of the data retention is according to the fitting between different temperature vsΔ in the literature. From the fitting, the thermal stability factorΔ is 55 transmitting to our working temperature 85 °C^[49], which satisfies the 10-years device storage requirements for 1 kb SOT MTJ array. There are two possible reasons for the relatively low chip-levelΔ. The first is the process variations mentioned above, and the process can be improved by further optimizing the lithography and etch process to minimize the damage to the free layers^[50]. The second is that we use a single 1.3 nm-thick CoFeB free layer in the current stack, which probably cannot provide a sufficient energy barrier if we peruse the Mb-level chip. Further stack engineering is required, such as changing the single CoFeB free layer to a double ferromagnetic or synthetic antiferromagnetic free layer design^[22].

In summary, we successfully demonstrated the capability of manufacturing in-plane field-free-switching SOT MTJ devices in the 200-mm-wafer platform. The devices exhibit low critical switching current density J_C ~ 40 MA/cm² at 100 ns, high TMR exceeding 100%, excellent thermal stabilityE_b > 50k_BT satisfying the 10-years device storage requirements and ultra-high endurance over 10¹⁰ cycles under 200-ns-pulses with current density of 58 MA/cm², which is 1.5 times large ofJ_C. Most importantly, decent variations of 18%, 7%, and 20% were achieved for the SOT channel resistanceR_SOT, MTJ resistance, and TMR ratios, respectively in 200-mm-wafer. The results encourage us to explore large size SOT MRAM arrays further. The large size SOT MRAM chips are suitable not only for the memory but also for hybrid CMOS/SOT MRAM logic applications, such as the in-memory computing field.

This work was supported by the National Key Research and Development Program of China (Grant Nos. 2021YFB3601303, 2021YFB3601304, 2021YFB3601300) and National Natural Science Foundation of China (Nos. 62001014 and 62171013)