• Infrared and Laser Engineering
  • Vol. 47, Issue 5, 520001 (2018)
Guo Zhiqiang1、2、*, Liu Liyuan1、2, and Wu Nanjian1、2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.3788/irla201847.0520001 Cite this Article
    Guo Zhiqiang, Liu Liyuan, Wu Nanjian. 12-bit compact multiple-columns-shared-parallel pipeline-SAR ADC for high speed CIS[J]. Infrared and Laser Engineering, 2018, 47(5): 520001 Copy Citation Text show less
    References

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    [2] Qu Hongsong, Zhang Ye, Jin Guang. Improvement of performance for CMOS area image sensors by TDI algorithm in digital domain[J]. Optics and Precision Engineering, 2010, 18(8): 1896-1903. (in Chinese)

    [3] Zou Mei, Chen Nan, Yao Libin. CMOS image sensor design with AC-coupled CTIA and digital CDS[J]. Infrared and Laser Engineering, 2017, 46(1): 0120002. (in Chinese)

    [4] Gao Lei, Zhai Yongcheng, Liang Qinghua, et al. IRFPA ROIC integrated digital output[J]. Infrared and Laser Engineering, 2015, 44(6): 1686-1691. (in Chinese)

    [5] Sun Honghai, Liu Yanying. Application and test of two different high-speed digital CMOS image sensors[J]. Chinese Optics, 2011, 4(5): 453-460. (in Chinese)

    [6] Kim Hyeon-June, Hwang Sun-Il, Kwon Ji-Wook. A delta-readout scheme for low-power CMOS image sensors with multi-column-parallel SAR ADCs[J]. IEEE Journal of Solid-State Circuits, 2016, 51(10): 2262-2273.

    [7] Funatsu Ryohei, Huang Steven, Yamashita Takayuki, et al. A 133 Mpixel 60 fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs[C]//IEEE International Solid-State Circuits Conference, 2015: 1-3.

    [8] Han Ye, Li Quanliang, Shi Cong, et al. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors[J]. Journal of Semiconductors, 2013, 34(8): 085016.

    [9] Li Quanliang, Liu Liyuan, Han Ye, et al. A 12-bit compact column-parallel SAR ADC with dynamic Power control technique for high-speed CMOS image sensors[J]. Journal of Semiconductors, 2014, 35(10): 132-139.

    [10] Tsai Shanju, Chen Yenchun, Hsieh Chih-Cheng, et al. A column-parallel SA ADC with linearity calibration for CMOS imagers[C]//IEEE Sensors, 2012: 1-4.

    [11] Jun D, Fumihiko T, Makoto Morimoto, et al. A187.5 μVrms-read-noise 51 mW 1.4 Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC[C]//IEEE International Solid-State Circuits Conference, 2013: 494.

    [12] Agnes A, Bonizzoni E, Maloberti. Design of an ultra-low power SA-ADC with medium/high resolution and speed[C]//IEEE International Symposium on Circuits & Systems, 2008: 1-4.

    [13] Gregoire B R, Moon U K. An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain[J]. IEEE Journal of Solid-State Circuits, 2008, 43(12): 2620-2624.

    Guo Zhiqiang, Liu Liyuan, Wu Nanjian. 12-bit compact multiple-columns-shared-parallel pipeline-SAR ADC for high speed CIS[J]. Infrared and Laser Engineering, 2018, 47(5): 520001
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