• Journal of Semiconductors
  • Vol. 42, Issue 3, 032401 (2021)
Liqiong Yang1,2, Linfeng Wang3, Junhua Xiao1,2, Longbing Zhang1,2, and Jian Wang1,2
Author Affiliations
  • 1State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
  • 2University of Chinese Academy of Sciences, Beijing 100049, China
  • 3Loongson Technology Corporation Limited, Beijing 100095, China
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    DOI: 10.1088/1674-4926/42/3/032401 Cite this Article
    Liqiong Yang, Linfeng Wang, Junhua Xiao, Longbing Zhang, Jian Wang. A 1.2 V, 3.1% 3σ-accuracy thermal sensor analog front-end circuit in 12 nm CMOS process[J]. Journal of Semiconductors, 2021, 42(3): 032401 Copy Citation Text show less
    Architecture of a typical thermal sensor.
    Fig. 1. Architecture of a typical thermal sensor.
    Analog front-end and new folded current unit.
    Fig. 2. Analog front-end and new folded current unit.
    (Color online) Simulation results for different numbers of folded stage used in BGR. (a) DC mismatch biased at the same current. (b) Worst variation of VBEN under 1.2 and 0.95 V, as obtained from a Monte Carlo simulation of 1000 runs.
    Fig. 3. (Color online) Simulation results for different numbers of folded stage used in BGR. (a) DC mismatch biased at the same current. (b) Worst variation of VBEN under 1.2 and 0.95 V, as obtained from a Monte Carlo simulation of 1000 runs.
    (Color online) Simulation results for flicker noise for normal CMOS and 4-stage folded structures.
    Fig. 4. (Color online) Simulation results for flicker noise for normal CMOS and 4-stage folded structures.
    (Color online) Die photo of the test chip.
    Fig. 5. (Color online) Die photo of the test chip.
    (Color online) Measured variation results for 2-VBE at room temperature.
    Fig. 6. (Color online) Measured variation results for 2-VBE at room temperature.
    (Color online) 3σ accuracy statistics for 200 chips, VBEP, VBEN, and VREF.
    Fig. 7. (Color online) 3σ accuracy statistics for 200 chips, VBEP, VBEN, and VREF.
    (Color online) Temperature linear results for VREF (calculated by the measured results of the variations of 2-VBE).
    Fig. 8. (Color online) Temperature linear results for VREF (calculated by the measured results of the variations of 2-VBE).
    ParameterRef. [7] Ref. [8] Ref. [9] Ref. [10] This work
    Technology130 nm CMOS350 nm CMOS180 nm CMOS7 nm CMOS12 nm CMOS
    Supply (V)0.751.21.21.3751.2
    Temprange (°C)–20 to 85–10 to 1100 to 110–45 to 125–40 to 130
    3σ (%)30.61.290.6<3.1
    TC (ppm)4012.7526688
    Of chips90000101077/200
    BJT onlyYesNoNoYesNo
    TypeSwitchCapDCDCDCDC
    Power (nW)17028.79.39.74 × 1054.96 × 104
    Area (mm2) 0.070.480.0550.0780.0124
    Table 1. Comparison table.
    Liqiong Yang, Linfeng Wang, Junhua Xiao, Longbing Zhang, Jian Wang. A 1.2 V, 3.1% 3σ-accuracy thermal sensor analog front-end circuit in 12 nm CMOS process[J]. Journal of Semiconductors, 2021, 42(3): 032401
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