Liqiong Yang, Linfeng Wang, Junhua Xiao, Longbing Zhang, Jian Wang. A 1.2 V, 3.1% 3σ-accuracy thermal sensor analog front-end circuit in 12 nm CMOS process[J]. Journal of Semiconductors, 2021, 42(3): 032401

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- Journal of Semiconductors
- Vol. 42, Issue 3, 032401 (2021)

Fig. 1. Architecture of a typical thermal sensor.

Fig. 2. Analog front-end and new folded current unit.

Fig. 3. (Color online) Simulation results for different numbers of folded stage used in BGR. (a) DC mismatch biased at the same current. (b) Worst variation of V BEN under 1.2 and 0.95 V, as obtained from a Monte Carlo simulation of 1000 runs.

Fig. 4. (Color online) Simulation results for flicker noise for normal CMOS and 4-stage folded structures.

Fig. 5. (Color online) Die photo of the test chip.

Fig. 6. (Color online) Measured variation results for 2-V BE at room temperature.

Fig. 7. (Color online) 3σ accuracy statistics for 200 chips, V BEP, V BEN, and V REF.

Fig. 8. (Color online) Temperature linear results for V REF (calculated by the measured results of the variations of 2-V BE).
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Table 1. Comparison table.

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