• Microelectronics
  • Vol. 52, Issue 2, 289 (2022)
CHIO U-Fat1, XIONG Deyu1, WANG Wei1, ZHANG Dingdong1, ZHANG Shan1, YUAN Jun1, YANG Zhenglin1, and LI Junfeng2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.210383 Cite this Article
    CHIO U-Fat, XIONG Deyu, WANG Wei, ZHANG Dingdong, ZHANG Shan, YUAN Jun, YANG Zhenglin, LI Junfeng. A 5 bit High Speed and Low Power Binary-Search ADC[J]. Microelectronics, 2022, 52(2): 289 Copy Citation Text show less
    References

    [1] OH D R, MOON K J, LIM W M, et al. An 8-bit 1-GS/s asynchronous loop-unrolled SAR-Flash ADC with complementary dynamic amplifiers in 28-nm CMOS [J]. IEEE J Sol Sta Circ, 2021, 56(4): 1216-1226.

    [2] CHUNG Y H, TSAI C H, YEH H C. A 5-b 1-GS/s 27-mW binary-search ADC in 90 nm digital CMOS [C]// IEEE Syst Chip Conf. Taipei, China. 2016: 25-29.

    [3] VAN DER PLAS G, VERBRUGGEN B. A 150 MS/s 133 μW 7 b ADC in 90 nm digital CMOS using a comparator - based asynchronous binary-search sub-ADC [C]// IEEE ISSCC. San Francisco, CA, USA. 2008: 242-243.

    [4] WONG S S, CHIO U F, CHAN C H, et al. A 48-bit ENOB 5-bit 500 MS/s binary-search ADC with minimized number of comparators [C]// IEEE ASSCC. Jeju, Korea. 2012: 73-76.

    [5] LIN Y Z, CHANG S J, LIU Y T, et al. An asynchronous binary-search ADC architecture with a reduced comparator count [J]. IEEE Trans Circ & Syst I: Regu Pap, 2010, 57(8): 1829-1837.

    [6] CHIO U F, SIN S W, SENG-PAN U, et al. A 5-bit 2 GS/s binary-search ADC with charge-steering comparators [C]// IEEE A-SSCC. Seoul, Korea. 2017: 221-224.

    [7] RAZAVI B. Charge steering: a low-power design paradigm [C]// IEEE Custom Integr Circ Conf. Los Angeles, CA, USA. 2013: 1-8.

    [8] TANAKA K, SAITO R, ISHIKURO H. A 16 GS/s 317 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration [C]// IEEE ESSCIRC. Yokohama, Japan. 2015: 327-330.

    [9] MURATORE D G, AKDIKMEN A, BONIZZONI E, et al. An 8-bit 07-GS/s single channel flash-SAR ADC in 65-nm CMOS technology [C]// IEEE ESSCIRC. Lausanne, Switzerland. 2016: 421-424.

    [10] CHANG K H, HSIEH C C. A calibration-free 12-bit 50-MS/s full-analog SAR ADC with feedback zero-crossing detectors [J]. IEEE J Sol Sta Circ, 2019, 54(6): 1-12.

    CHIO U-Fat, XIONG Deyu, WANG Wei, ZHANG Dingdong, ZHANG Shan, YUAN Jun, YANG Zhenglin, LI Junfeng. A 5 bit High Speed and Low Power Binary-Search ADC[J]. Microelectronics, 2022, 52(2): 289
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