A high speed and low power binary-search ADC was designed in a 65 nm CMOS technology. Compared with the traditional binary-search architecture, the employed comparator was composed of a two-stage dynamic preamplifier and a one-stage dynamic latch, which reduced the static current and achieved extremely low power consumption. The offset voltage was reduced to a level that do not cause decision error, and the external digital calibration module was omitted. As a result, the chip area was reduced, and calibration accessories were avoided to slow down the comparator. The post-simulation results showed that the effective bit of the binary-search ADC reached 4.59 bit, and the power consumption was only 1.57 mW at 1 GHz sampling frequency.