A MASH Architecture 24 bit Σ- A/D Converter

SHEN Xiaofeng; LI Liang; FU Dongbing; WANG Youhua; ZHU Can

doi:10.13911/j.cnki.1004-3365.zjea004

[1] SCHREIER R, TEMES G C. Understanding delta-sigma data converters ［M］. Piscataway: IEEE Press, 2005.

[2] BAIRD R, FIEZ T S. Stability analysis of high order delta-sigma modulation for ADC ［J］. IEEE Trans Circ & Syst II: Anal Dig Signal Process, 1994, 41(1): 59-62.

[3] MAGHARI N, MOON U K. Multi-loop efficient sturdy MASH delta-sigma modulators ［C］// IEEE Int Symp Circ & Syst. Seattle, WA, USA. 2008: 1216-1219

[4] MAGHARI N, WON S K, TEMES G, et al. Sturdy mash -Σ modulator ［J］. Elec Lett, 2006, 42(22): 1269-1270.

[5] KUSUDA Y. Auto correction feedback for ripple suppression in a chopper amplifier ［J］. IEEE J Sol Sta Circ, 2010, 45(8): 1436-1445.

[7] ROMBOUTS P, DE MAEYER J, WEYTEN L. Design of double-sampling Σ modulation A/D converters with bilinear integrators ［J］. IEEE Trans Circ Syst I: Regu Pap, 2005, 52(4): 715-722.

[8] ROMBOUTS P, WEYTEN L. Systematic design of double-sampling Σ A/D converters with a modified noise transfer function ［J］. IEEE Trans Circ Syst II: Expr Bri, 2004, 51(12): 675-679.

[9] FOGLEMAN E, GALTON I, HUFF W, et al. A 33-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SNDR ［J］. IEEE J Sol Sta Circ, 2000, 35(3): 297-307.

[10] WANG B N, ISHIZUKA S, LIU Y. A 113-dB DSD audio ADC using a density-modulated dithering scheme ［J］. IEEE J Sol Sta Circ, 2003, 38(1): 114-119.

[11] FUJIMORI I, KOYAMA K, TRAGER D, et al. A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range ［J］. IEEE J Sol Sta Circ, 1997, 32(3): 329-336.