A MASH Architecture 24 bit Σ- A/D Converter

SHEN Xiaofeng; LI Liang; FU Dongbing; WANG Youhua; ZHU Can

doi:10.13911/j.cnki.1004-3365.zjea004

Journals >Microelectronics >Volume 52 >Issue 2 >Page 223 > Article

Microelectronics
Vol. 52, Issue 2, 223 (2022)

A MASH Architecture 24 bit Σ- A/D Converter

SHEN Xiaofeng^1、2, LI Liang^1、2, FU Dongbing^1、2, WANG Youhua^1、2, and ZHU Can^1、2

Author Affiliations

¹[in Chinese]

²[in Chinese]

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DOI: 10.13911/j.cnki.1004-3365.zjea004 Cite this Article

SHEN Xiaofeng, LI Liang, FU Dongbing, WANG Youhua, ZHU Can. A MASH Architecture 24 bit Σ- A/D Converter[J]. Microelectronics, 2022, 52(2): 223 Copy Citation Text

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Abstract

A discrete-time Σ- A/D converter was presented. The A/D converter was based on the cascade noise shaping (MASH) structure design. The whole converter was composed of programmable gain amplifier, cascade modulator and digital decimation filter. The A/D converter was implemented in a standard 018 μm CMOS technology, and the chip area was 6 mm2. Test results showed that the A/D converter had an SNR of 106 dB, an SFDR of 110 dB, a power consumption of only 20 mW at 16 kS/s output data rate.

Keywords

cascade MASH double-sampling noise shaping Σ- A/D converter Σ- modulator

SHEN Xiaofeng, LI Liang, FU Dongbing, WANG Youhua, ZHU Can. A MASH Architecture 24 bit Σ- A/D Converter[J]. Microelectronics, 2022, 52(2): 223

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