• Journal of Semiconductors
  • Vol. 44, Issue 4, 040301 (2023)
Yan Lu*, Guigang Cai*, and Junwei Huang*
Author Affiliations
  • State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao, China
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    DOI: 10.1088/1674-4926/44/4/040301 Cite this Article
    Yan Lu, Guigang Cai, Junwei Huang. Favorable basic cells for hybrid DC–DC converters[J]. Journal of Semiconductors, 2023, 44(4): 040301 Copy Citation Text show less

    Abstract

    With the surging demands for extremely high current at sub-1 V supply voltage level in high performance computing and autonomous driving, high density power delivery becomes one of the critical limiting factors for system integration. 48 V power bus system is emerging for these high current applications to reduce the IR losses on the power delivery networks. Thus, there is a wide voltage gap between the power bus and the digital supply rails at the point-of-load (PoL), calling for novel power conversion topologies and system architectures. Although the performances of the integrated power circuits heavily depend on both the quality factor of passive components and the figure-of-merit (FoM) of active devices, a smart circuit designer should also find an optimum way to guide the currents and to deliver the power.

    To bridge this gap, switched-capacitor-inductor (SCI) hybrid DC–DC converter, started from the double step-down buck converter[1,2], has been the hottest topic in the power management IC area in the past 5 years or so. Researchers from different groups proposed tens of innovative topologies[3-8] and several efficient operation schemes[9], and summarized design guidelines[10]. The basic idea of a hybrid converter is to use switched-capacitor (SC) cells to reduce the voltage swing on the power inductor such that a smaller inductor can be used. On the other hand, it brings the drawback of slow transient response as the inductor current slew rate also becomes smaller[11]. In this letter, we would like to share several of our observations and design suggestions. With that, we may build new hybrid DC–DC converters like building a “Golden-Gate Bridge” with basic circuit cells.

    A simple way to invent a new hybrid DC–DC topology

    We can obtain a new (but not necessarily new) hybrid converter by replacing any one of the switches in an SC converter with a power inductor[12]. Then, the SC converter becomes a hybrid converter! Furthermore, we can also replace two switches with two power inductors. Again, a new hybrid converter!!

    But, with two or more inductors, we should not establish a state with two inductors in series which will generate unwanted energy loss, similar to the charge redistribution loss when two capacitors connect in parallel. And of course, circuit designers still need to analyze the voltage conversion ratio, small-signal transfer function, switch voltage stresses and inductor current stresses of the new hybrid converter. Although some SC converters could be very complicated with many switches and capacitors, eventually, only a handful of topologies would make sense and be suitable for a targeted application.

    Next, let us discuss what would be the favorable basic circuit cells and building blocks for a switched-capacitor-inductor hybrid DC–DC converter (Fig. 1).

    The basic circuit cells and building blocks of a hybrid DC–DC converter.

    Figure 1.The basic circuit cells and building blocks of a hybrid DC–DC converter.

    One good low-side power switch

    For large voltage conversion ratio step-down DC–DC conversion, when one side of the power inductor connects to the output node, the other side would usually be switched to the ground for most of the time. Therefore, the circuit cell with a single switch that connects the power inductor to the ground is a must-have for high efficiency. We can see several of these good examples in recent ISSCC papers[13-15]. Meanwhile, transistor stacking technique can be easily applied here to withhold high voltage stress with two or more low-voltage transistors, improving the switch’s figure-of-merit (FoM)[16].

    Series capacitor(s) on the high-side

    Series capacitor(s) on the high-side is for reducing the power inductor voltage stress[17,18]. For a very large VCR, multiple capacitors may be involved. Therefore, from the topology selection perspective, the high-side part has the most variations. There are several considerations in selecting the high-side series capacitor topology. One major concern is the voltage ratings of the capacitor(s) and the switches. High-voltage capacitor has much less energy density while connecting two or more capacitors in series also results in smaller equivalent capacitance. As the voltage ratings of the capacitors and switches are technology process dependent, and only has limited selections, the high-side series capacitor topology design is highly related to the available component voltage ratings. Bootstrap circuit and intermediate voltage rail designs are also very important for reducing the silicon area and optimizing the switching losses[19].

    Hard charging is not necessarily a bad thing

    When two capacitors with different voltages exchange charges in an SC converter, a high peak initial current would happen, diminishing the benefit of smaller RON of the switches. Conventionally, hard charging is considered as a disadvantage, as it is the root cause for the inherent charge redistribution loss of an SC converter. However, hard charging has two advantages. First, hard charging provides large output current to the load, as there is no current limiting component (inductor) on the current path. As capacitors generally have larger energy storage density compared to inductors, we can have large capacitance to reduce the dV on the capacitors and to mitigate the hard charging loss[20]. Second, hard charging provides instant response to output voltage change[21]. When output voltage drops, the output current increases proportionally, alleviating the shortcoming (slow transient response with reduced inductor voltage) of hybrid DC–DC converters.

    Resonant SC operation helps the efficiency

    In a resonant switched-capacitor operation, the resonant inductor shapes its current waveform into quasi-sinusoidal, reducing the root-mean-square (RMS) current when conducting the same average current[22,23]. To deliver the same amount of power, resonant SC can operate at a lower frequency when compared to an SC converter. On the other hand, the resonant inductor also limits the instant output current, and its DCR adds conduction loss. Usually, the value of a resonant inductor is much smaller than that of the power inductor in a typical buck converter, so its DCR can be negligible. Overall, resonant SC operation may help to improve the conversion efficiency but would not improve the power density.

    High output current, multiple paths, multiple inductors

    Over the past two decades, single-inductor multiple-output DC–DC converter has also been a very popular research topic[24]. However, when it comes to high current applications, the high current stress on the power inductor forces people to use multiple inductors. In the past year, a few multiple-inductor and multiple-output converters have been proposed for high current applications[25-27].

    In summary, SCI hybrid DC–DC converter provides plenty of room for innovations and performance improvements. With the suggested design considerations given in this letter, we may easily build hybrid DC–DC converters with favorable basic circuit cells. Looking forward, we see that hybrid DC–DC converters may also find their applications in multiple-output and 3D integration scenarios.

    References

    [1] K Nishijima, K Harada, T Nakano et al. Analysis of double step-down two-phase buck converter for VRM. INTELEC 05 - Twenty-Seventh International Telecommunications Conference, 497(2005).

    [2] P S Shenoy, O Lazaro, R Ramani et al. A 5 MHz, 12 V, 10 A, monolithically integrated two-phase series capacitor buck converter. 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), 66(2016).

    [3] A Abdulslam, P P Mercier. A continuous-input-current passive-stacked third-order buck converter achieving 0.7W/mm2 power density and 94% peak efficiency. 2019 IEEE International Solid- State Circuits Conference (ISSCC), 148(2019).

    [4] K Hata, Y Yamauchi, T Sai et al. 48V-to-12V dual-path hybrid DC-DC converter. 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 2279(2020).

    [5] Z C Ye, R A Abramson, R C N Pilawa-Podgurski. A 48-to-6 V multi-resonant-doubler switched-capacitor converter for data center applications. 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 475(2020).

    [6] Z Y Xia, J Stauth. A two-stage cascaded hybrid switched-capacitor DC-DC converter with 96.9% peak efficiency tolerating 0.6V/μs input slew rate during startup. 2021 IEEE International Solid- State Circuits Conference (ISSCC), 256(2021).

    [7] Z Tong, J Huang, Y Lu et al. A 42W reconfigurable bidirectional power delivery voltage-regulating cable. IEEE International Solid-State Circuit Conference (ISSCC), 192(2023).

    [8] C Hardy, H P Le. A 21W 94.8%-efficient reconfigurable single-inductor multi-stage hybrid DC–DC converter. IEEE International Solid-State Circuit Conference (ISSCC), 190(2023).

    [9] P Renz, M Kaufmann, M Lueders et al. A fully integrated 85%-peak-efficiency hybrid multi ratio resonant DC-DC converter with 3.0-to-4.5V input and 500μA-to-120mA load range. 2019 IEEE International Solid- State Circuits Conference (ISSCC), 156(2019).

    [10] P H McLaughlin, J S Rentmeister, M H Kiani et al. Analysis and comparison of hybrid-resonant switched-capacitor DC–DC converters with passive component size constraints. IEEE Trans Power Electron, 36, 3111(2021).

    [11] C H Chan, L Cheng, W Deng et al. Trending IC design directions in 2022. J Semicond, 43, 071401(2022).

    [12] S W Zhen, R Yang, D M Wu et al. Design of hybrid dual-path DC-DC converter with wide input voltage efficiency improvement. 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1(2021).

    [13] X Yang, H X Cao, C K Xue et al. An 8A 998A/inch3 90.2% peak efficiency 48V-to-1V DC-DC converter adopting on-chip switch and GaN hybrid power conversion. 2021 IEEE International Solid- State Circuits Conference (ISSCC), 466(2021).

    [14] X Yang et al. A 5A 94.5% peak efficiency 9~16V-to-1V dual-path series-capacitor converter with full duty range and low V·A metric. IEEE International Solid-State Circuit Conference (ISSCC), 196(2023).

    [15] W Zeng, G Cai, C Lee et al. A 12V-input 1V–1.8V-output 93.7% peak efficiency dual-inductor quad-path hybrid DC–DC converter. IEEE International Solid-State Circuit Conference (ISSCC), 200(2023).

    [16] C Schaef, S Weng, B Choi et al. A 93.8% peak efficiency, 5V-input, 10A max ILOAD flying capacitor multilevel converter in 22nm CMOS featuring wide output voltage range and flying capacitor precharging. 2019 IEEE International Solid-State Circuits Conference (ISSCC), 146(2019).

    [17] K Wei, Y Ramadass, D B Ma. A direct 12V/24V-to-1V 3W 91.2%-efficiency tri-state DSD power converter with online VCF rebalancing and In-situ precharge rate regulation. 2020 IEEE International Solid-State Circuits Conference (ISSCC), 190(2020).

    [18] Y Yamauchi, T Sai, K Hata et al. 0.55 W, 88%, 78 kHz, 48 V-to-5 V fibonacci hybrid DC–DC converter IC using 66 mm3 of passive components with automatic change of converter topology and duty ratio for cold-crank transient. IEEE Trans Power Electron, 36, 9273(2021).

    [19] T X Hu, M Huang, Y Lu et al. A 4A 12-to-1 flying capacitor cross-connected DC-DC converter with inserted D>0.5 control achieving >2x transient inductor current slew rate and 0.73 × theoretical minimum output undershoot of DSD. 2022 IEEE International Solid- State Circuits Conference (ISSCC), 1(2022).

    [20] J Y Ko, Y Huh, M W Ko et al. A 4.5V-input 0.3-to-1.7V-output step-down always-dual-path DC-DC converter achieving 91.5%-efficiency with 250mΩ-DCR inductor for low-voltage SoCs. 2021 Symposium on VLSI Circuits, 1(2021).

    [21] G G Cai, Y Lu, R P Martins. An SC-parallel-inductor hybrid buck converter with reduced inductor voltage and current. IEEE J Solid State Circuits, 1(2022).

    [22] K Kesarwani, R Sangwan, J T Stauth. Resonant-switched capacitor converters for chip-scale power delivery: Design and implementation. IEEE Trans Power Electron, 30, 6966(2015).

    [23] G Cai, Y Lu, R P Martins. A compact 12V-to-1V 91.8% peak efficiency hybrid resonant switched-capacitor parallel inductor (ReSC-PL) buck converter. IEEE International Solid-State Circuit Conference (ISSCC), 198(2023).

    [24] T H Yang, Y H Wen, Y J Ouyang et al. A 0.03mV/mA low crosstalk and 185nA ultra-low-quiescent single-inductor multiple-output converter assisted by 5-input operational amplifier for 94.3% peak efficiency and 3.0W driving capability. 2021 IEEE International Solid- State Circuits Conference (ISSCC), 267(2021).

    [25] H Han, M W Ko, J H Cho et al. A monolithic 48V-to-1V 10A quadruple step-down DC-DC converter with hysteretic copied on-time 4-phase control and 2 × slew rate all-hysteretic mode. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 182(2022).

    [26] T Hu, M Huang, Y Lu et al. A 12V-to-1V quad-output switched-capacitor buck converter with shared DC capacitors achieving 90.4% peak efficiency and 48mA/mm3 power density at 85% efficiency. IEEE International Solid-State Circuit Conference (ISSCC), 184(2023).

    [27] W Hung, C Chen, Y Huang et al. A double step-down dual-output converter with cross regulation of 0.025mV/mA and improved current balance. IEEE International Solid-State Circuit Conference (ISSCC), 188(2023).

    Yan Lu, Guigang Cai, Junwei Huang. Favorable basic cells for hybrid DC–DC converters[J]. Journal of Semiconductors, 2023, 44(4): 040301
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