• Microelectronics
  • Vol. 52, Issue 1, 1 (2022)
LIU Junhong1, LUO Ping1、2, ZHAO Zhong1, YANG Bingzhong1, and CAO Qi1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.210293 Cite this Article
    LIU Junhong, LUO Ping, ZHAO Zhong, YANG Bingzhong, CAO Qi. Design of a High Efficiency Buck Converter[J]. Microelectronics, 2022, 52(1): 1 Copy Citation Text show less

    Abstract

    A high-efficiency buck converter circuit was designed in a 0.35 μm BCD process, with 10 V~24 V input voltage, 5 V~12 V output voltage, and 100 mA load current. A simple circuit structure based on the hysteresis control was presented. And the fewer power consumption of the buck converter was achieved by using the sleep mode. In the active mode, the quiescent current was about 110 μA, and in the sleep mode, the quiescent current was about 11 μA. For the phenomenon that the switching loss accounted for a larger proportion under light load conditions, a floating gate voltage circuit for the synchronous power MOSFET MN was designed to reduce the switching loss. Simulation results showed that with 10 V input and 5 V output, the efficiency could reach 67.7% under 0.1 mA load, and the efficiency was higher than 91% above 10 mA load.
    LIU Junhong, LUO Ping, ZHAO Zhong, YANG Bingzhong, CAO Qi. Design of a High Efficiency Buck Converter[J]. Microelectronics, 2022, 52(1): 1
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