Based on the SMIC 0.18 μm CMOS process, a reconfigurable second-order Σ-Δ modulator was designed for the applications of adaptive systems. With the introduction of dynamic voltage scaling technique, how to reduce the power supply voltage to save ADC power consumption under different input signals had been studied. First, the effects of non-ideal parameters on system performance had been analyzed by mathematical modeling under Simulink, and then the circuit design had been conducted under Cadence, with the layout design and post-simulation completed. In addition to conventional adjustment schemed such as the op amp’s input differential pair width-to-length ratio and tail current, the power supply voltage could be adjusted according to the input signal amplitude to further improve the system flexibility. The simulation results showed that if the ENOB required by the system was 12 bit, the modulator’s power consumption was reduced from 123 μW to 51 μW when the power supply voltage was decreased from 3.3 V to 1.8 V, indicating a significant power saving effect. The area of the designed modulator’s layout was 0.06 mm2.