Abstract
1. Introduction
Digital to analog converters (DAC) are circuits that converse signals with information in bits to signals with information in their amplitude and time domain characteristics[
Due to the increasing demand for higher data rates, transmitters[
In the design of current steering DACs, the main challenge is to reduce the impact of static and dynamic errors. The static errors mainly come from the amplitude mismatch of current sources[
As the sampling rate and signal frequency increases, the dynamic errors begin to dominate. The dynamic errors include finite output impedance[
With the continuous development of IC design and process technology, a series of high-speed high-resolution DACs have been reported with a higher sampling rate, higher resolution, better performance, and lower power consumption. In Fig. 1, a comparison is made with the spurious free dynamic range (SFDR) performance versus sampling rate of high-speed high-resolution DACs published in the top conferences and journals in recent years.
Figure 1.(Color online) Performance comparison of state-of-the-art DACs: SFDR@1GHz vs. sampling rate.
Table 1 shows a more detailed performance summary and comparison with these state-of-the-art high-speed high-resolution current steering DACs. Figs. 2(a)–2(c) show the comparison of three common figures of merit (FoM) versus sampling rate with detailed definitions of the FoMs are given in Table 2.
Figure 2.(Color online) Performance comparison of state-of-the-art DACs: (a) FoM1, (b) FoM2, (c) FoM3 versus sampling rate.
Table Infomation Is Not EnableThis paper aims to provide a survey of cutting-edge high-speed high-resolution DACs with the mainstream technologies in circuit implementations. The rest of this paper is organized as follows. Section 2 presents a roughly description about the architecture of the current steering DACs. Section 3 outlines the dominating techniques in the subcircuit design, including the encoding segmentation, switching current source and the switch driver. Section 4 introduces the calibration and error reducing techniques for static and dynamic errors. The summary is given in Section 5.
2. Architecture of high-speed high-resolution DACs
The block diagram of a traditional high-speed high-resolution current steering DAC is shown in Fig. 3. In such an architecture, the input digital signal (binary bits) can be covert into unary bits by the thermometer encoder, or go through a delay equalizer to align the data stream for the segmented encoding. If a higher sampling rate is needed, multiplexers (MUX) can be introduced before or after the encoder[
Figure 3.(Color online) Block diagram of a high-speed high-resolution current steering DAC with a typical switching current cell.
3. Subcircuit design
3.1. Encoding and segmentation
Encoder is one of the critical subcircuits. As mentioned before, a suitable encoding method is important for higher linearity design. According to the different current weights of current-steering cells, there are three encoding architectures of current steering DAC: binary-weighted architecture[
Since the digital input of DAC is binary codes, the binary-weighted architecture is the most intuitive way. Refs. [18, 20] reveal that the advantages of this architecture are its simplicity. However, with the increase of N (resolution), the MSB-controlled current source differs greatly from the current source controlled by the least significant bits (LSB). To be precise, the maximum current is 2N–1 times that of the minimum current[
The thermometer-weighted (unary-weighted) architecture is another option, which means that all switching currents have the same weight. This architecture can bring less disturbances on the output signal[
Generally speaking, the segmented architecture is the preferred one to combine the advantages of above architectures: the coarse bits use thermometer-type coding to reduce the requirements on matching and improve the linearity, while the fine bits using binary coding to reduce the complexity of current cells. As a result, the most important trade-off is the segment ratio[
Large coarse bits will introduce more parasitic capacitance, while large fine bits bringing the mismatch of current cells at the border. In Ref. [47], a design procedure of segmentation is outlined. The matching accuracy of the current source can be estimated based on the size of the transistors. After that, the maximum number of LSB section is determined according to the estimation and the yield requirements. Ref. [49] builds a model with the bandwidth and SFDR represented as a function of segmentation ratio for its hybrid DAC. Ref. [17] chooses a 6–10 segmentation in combination with the bounded INL calibration for a 16-bit DAC. In Ref. [35], the incoming data is decoded to the 3–3–3–5 (unary–unary–unary–binary) segmentation for a compact layout. In short, the segmentation design is not constant for a specific resolution, a compromise between good static and dynamic specifications versus power and area should be found[
3.2. Switching current source cell design
In current steering DACs, the performance of switching current source determines the performance of the DAC. A typical structure of the switching current source cell is shown in Fig. 4, which contains a cascoded current source, differential current switches, thick-oxide output cascodes and bleeding currents[
Figure 4.A typical switching current cell proposed in Ref. [
As discussed earlier, the finite output impedance of the current source is one of the important factors that affect the dynamic performance. For this reason, the thick-oxide cascode devices (M4/M5) are added between the switch (M2/M3) and the output node to reduce the effect at low frequencies[
Figure 5.Quad-switching current cell with switch cascodes reported in Ref. [
In the design of switching current source cell, it is crucial to reduce the signal-dependence of switch behavior[
Ref. [34] proposed a quad-switch as presented in Fig. 6, using two pairs of differential switches, which are activated alternately in every clock cycle. Even if there is no data change, the switching event will occur. The code-independent switching event improves the distortion performance at high frequency. Engel et al.[
Figure 6.A simplified quad-switch cell proposed in Ref. [
RZ switch is also an effective method to reduce the signal-dependent nonlinearity, as it can insert a zero output state between two consecutive signals[
Figure 7.RZ current cell with resampling switches proposed in Ref. [
Figure 8.(Color online) Magnitude of the frequency response for NRZ, RZ, and MRZ waveforms reported in Ref. [
3.3. Switch driver circuit design
The switch driver is the transition cell from the digital domain to the analog domain[
Ref. [21] proposed a typical switch gate driving, which creates a steep transition and has a short clock-to-output delay. This structure, as shown in Fig. 9, is also applied in Refs. [2, 56]. This pseudo-differential CMOS latch has advantages on driving the analog current source cell directly, and providing the final timing for the data input of the current source cells. To accelerate the signal transition further, PMOS transistors are added in Ref. [57], getting the capability of both pull-up and pull-down. The simplified schematic of the high-speed latch is demonstrated in Fig. 10, while the similar structure demonstrated in Fig. 11 may produce faster rise/fall times owing to the devices M1–M4[
Figure 9.A typical fast latch proposed in Ref. [
Figure 10.High-speed latch presented in Ref. [
Figure 11.DAC output stack, with the switch driver proposed in Ref. [
For the switch driver design, a critical problem is the mismatch of the signal-dependent switching timing. The latches driving the current source cells are intrinsically nonstatic, and the signal generated by the final latches will produce supply ripples[
Figure 12.Block diagram of dummy trigger proposed in Ref. [
Erdmann et al.[
Ravinuthula et al.[
In addition, the CML latch configuration is commonly used for low-swing differential operation at high frequencies and small disturbance on the power supply. A master–slave CML latch was applied in Ref. [58]. The digital output of the encoder will be latched first by master latches, then by slave latches, as shown in Fig. 13. The usage of two latch stages enables precise timing and steep edges to minimize the timing errors. The double-edge switch driver can be introduced to reduce the input clock frequency, and one of its major drawbacks is the memory effect, or the inter-symbol interference (ISI). Since the last operation may affect the next working state, Ref. [59] adds reset transistors to the common source node of the CML switch driver to form an enhanced reset circuit in a 14-bit 8GS/s DAC. As depicted in Fig. 14, when one branch is in off state, the associated reset transistor charges the common node to a fixed voltage.
Figure 13.Master-slave latch presented in Ref. [
Figure 14.Double-edge current switch driver with enhanced reset circuit reported in Ref. [
4. Calibration and error reducing techniques
4.1. Static error calibration techniques
In current steering DACs, the main goal of static error calibration is reducing the amplitude mismatch between current sources.
Calibration techniques can be divided into foreground calibration[
While the foreground calibration is performed only once, the background retriggers the current cell periodically. It not only eliminates the static mismatch, but also tracks the error slow varying with time, which is related to the bias conditions and chip temperature fluctuations[
Another attractive option for static error calibration is the foreground calibration technique. A successive approximation register (SAR) logic and a CAL_DAC can be introduced[
The main constraints of the foreground calibration techniques are their sensitivity to the temperature and supply voltage variations. To track the current source mismatch change with temperature, Zhu et al.[
where I is the nominal bias current and
However, the scheme explained above only considers the main component of the mismatch current. For greater accuracy, Zhu et al.[
Figure 15.Two-parameter calibration loop configuration and CAL_DACs proposed in Ref. [
4.2. Dynamic error reducing techniques
With the improvement of the sampling rate and output bandwidth, the dynamic errors become more dominant on the high frequency performance. The DEM technique[
DEM technique is an effective technique which can suppress both static and dynamic errors. Its principle is to select the circuit cell by randomization, which refers to the random permutation of switches[
RZ technique has been mentioned in Section 3.2, which means that the output tracks the signal once it has settled and then returns to zero. A typical RZ switching current cell was presented in Fig. 7 and the ideal RZ output is a square waveform composed of the signal value and zero in a clock cycle[
DEM and DRZ can be used in combination[
The layout arrangement technique is also a significant option to mitigate the systematic matching errors. To reduce the timing skew induced between current cells, Ref. [35] applied the Q2 random walk arrangement with a common centroid proposed in Ref. [64], and then described a novel method named concentric parallelogram routing (CPR). The routing lengths used to connect the sub-cells can be equal, achieving a lower gradient mismatch error. In Ref. [53], a vertically stacked tree (VST) structure forms an H-tree for each cell was proposed to provide identical path lengths to the output summing node, thereby minimizing variations in amplitude and phase.
A number of excellent dynamic error reducing techniques are proposed in recent years. To break the linearity limitation of Nyquist DAC, a hybrid DAC architecture with a Nyquist path and an oversampling path was proposed by Su et al.[
Figure 16.Conceptual block diagram of a dual-rate hybrid DAC architecture proposed in Ref. [
To mitigate the data-dependent switching distortions, a random pairwise swapping (RPS) technique was proposed in Ref. [68], which reduces the intermodulation distortions between the element transition rate and the output-dependent unit switching. RPS randomly swaps the switching control signals of paired switching units in the random DEM decoding, resulting a 5–12 dB SFDR improvement at 1.0 GS/s.
To remedy the finite output impedance effect at high frequencies, an output impedance compensation (OIC) technique was proposed in Ref. [35], which introduces a data-dependent compensation resistor, Rcp(Din). The current induced by the Rcp changes the current through the load resistors for compensating the distortion. The Rcp can be approximated by a PMOS biased with a data-dependent gate voltage VG(Din), as shown in Fig. 17. Notably, the OIC technique enables the use of non-cascoded current cells. A 14-bit 10 GS/s DAC with > 65 dBc SFDR over the entire Nyquist bandwidth was achieved by using the simple PMOS-based Rcp(Din) with two-level VG(Din).
Figure 17.OIC technique with compensation resistor proposed in Ref. [
5. Conclusion
Nowadays high-speed high-resolution DACs have been widely applied. In 5G communication, optical communication, and more broadband applications, the DAC becomes a bottleneck that limits the performance of the system. The state-of-the-art high-speed high-resolution current steering DACs are reviewed in this paper, with focus on the subcircuit design and error reducing techniques. Comparisons are made between different architectures, circuit implementations and calibration techniques along with three common FoM results.
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