• Microelectronics
  • Vol. 51, Issue 1, 112 (2021)
LIU Yukui1, YIN Wanjun1, TAN Kaizhou1、2, and CUI Wei1、2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.200322 Cite this Article
    LIU Yukui, YIN Wanjun, TAN Kaizhou, CUI Wei. Study on Differential Negative Resistance of Submicron ESD-Implanted NMOS IDT-VGS Under High Electric Field[J]. Microelectronics, 2021, 51(1): 112 Copy Citation Text show less
    References

    [1] DUVVURY C. ESD: design for IC chip quality and reliability [C] // Proceed IEEE 1st ISQED. San Jose, CA, USA. 2000: 251-259.

    [2] VASHCHENKO V A, CONCANNON A, TER BEEK M, et al. ESD-implant effect on protection capabiliy of NMOS structures [C] // Proc ESSDERC. Estoril, Portugal. 2003: 565-568.

    [3] KER M D, CHEN W Y, SHIEH W T, et al. New ballasting layout schemes to improve ESD robustness of I/O buffers in fully silicided CMOS process [J]. IEEE Trans Elec Dev, 2009, 56(12): 3149-3159.

    [4] DUVVURY C. ESD protection device issues for IC designs [C] // IEEE CCIC. San Diego, CA, USA. 2001: 41-48.

    [5] CHEN J, AMERASEKERA A, DUVVURY C. Design methodology and optimization of gate-driven nMOS ESD protection circuits in submicron CMOS processes [J]. IEEE Trans Elec Dev, 1998, 45(12): 2448-2456.

    [6] KER M D, CHEN T Y. Substrate-triggered ESD protection circuit without extra process modification [J]. IEEE J Sol Sta Circ, 2003, 38(2): 295-302.

    [7] DU F B, SONG S Y, HOU F,et al. An enhanced gate-grounded NMOSFET for robust ESD applications [J]. IEEE Elec Dev Lett, 2019, 40(9): 1491-1494.

    [8] VITTOZ E A. MOS transistors operated in the lateral bipolar mode and their applications in CMOS technology [J]. IEEE J Sol Sta Circ, 1983, SC-18(3): 273-279.

    [9] HSUF C, KO P K, TAM S, et al. An analytical breakdown model for short-channel MOSFET’s [J]. IEEE Trans Elec Dev, 1982, 29(11): 1735-1740.

    LIU Yukui, YIN Wanjun, TAN Kaizhou, CUI Wei. Study on Differential Negative Resistance of Submicron ESD-Implanted NMOS IDT-VGS Under High Electric Field[J]. Microelectronics, 2021, 51(1): 112
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