[1] SIRAGUSA E, GALTON I. A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC ［J］. IEEE J Sol Sta Circ, 2004, 39(12): 2126-2138.

[2] MEHR I, SINGER L. A 55-mW, 10-bit, 40-MSample/s Nyquist-rate CMOS ADC ［J］. IEEE J Sol Sta Circ, 2000, 35(3): 318-325.

[3] SAHOO B D, RAZAVI B. A 12-bit 200-MHz CMOS ADC ［J］. IEEE J Sol Sta Circ, 2009, 44(9): 2366-2380.

[4] YU P C, LEE H S. A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC ［J］. IEEE J Sol Sta Circ, 1996, 31(12): 1854- 1861.

[5] LEE B G, TSANG R M. A 10-bit 50 MS/s pipelined ADC with capacitor-sharing and variable-gm opamp ［J］. IEEE J Sol Sta Circ, 2009, 44(3): 883-890.

[6] LI J, ZENG X Y, XIE L, et al. A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications ［J］. IEEE J Sol Sta Circ, 2008, 43(2): 321-329.

[7] NAGARAJ K, FETTERMAN H S, ANIDJAR J, et al. A 250-mW, 8-b, 52-MSamples/s parallel-pipelined A/D converter with reduced number of amplifiers ［J］. IEEE J Sol Sta Circ, 1997, 32(3): 312-320.

[8] LEE B G, MIN B M, MANGANARO G, et al. A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC ［J］. IEEE J Sol Sta Circ, 2008, 43(12): 2613-2619.

[9] CHANG D Y. Design technique for a pipelined ADC without using a front-end sample-and-hold amplifier ［J］. IEEE Trans Circ Syst I: Regu Pap, 2004, 51(11): 2123-2132.

[10] CHANG D Y, MOON U K. A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique ［J］. IEEE J Sol Sta Circ, 2003, 38(8): 1401-1404.

[11] IROAGA E, MURMANN B. A 12-bit 75-MS/s pipelined ADC using incomplete settling ［J］. IEEE J Sol Sta Circ, 2007, 42(4): 748-756.