A 14-bit 85 MS/s pipelined analog-to-digital converter (ADC) was designed and implemented in a 0.18 μm CMOS process. Several techniques such as SHA-less front-end and amplifier sharing had been adopted to reduce the ADC’s power consumption and area. Under 3.3 V power supply, 85 MHz clock and 70 MHz sine input, the ADC achieved an SNR of 67.9 dBFS and an SFDR of 82.2 dBFS without calibration. It consumed 322 mW with an area of 0.6 mm2, which was suitable for communication systems where lower power ADCs were needed.