Research on MDAC Capacitance Mismatch Calibration Based on Pipelined ADC

LI Kun; YE Mingyuan; WAN Shuqin; HE Qiuxiu

doi:10.13911/j.cnki.1004-3365.zjea011

[2] SHI L, ZHAO W, WU J, et al. Digital background calibration techniques for pipelined ADC based on comparator dithering ［J］. IEEE Trans Circ & Syst II: Expr Bri, 2012, 59(4): 239-243.

[3] YU P C, SHEHATA S, JOHARAPURKAR A, et al. A 14 b 40 MSample/s pipelined ADC with DFCA ［C］// IEEE ISSCC. San Francisco, CA, USA. 2001: 136-137.

[4] LI H, LI R, HU B Y, et al. A background calibration technology for capacitance mismatch in pipelined ADCs with 2.5-bit/stage MDAC ［C］// 13th IEEE ICSICT. Hangzhou, China. 2016: 924-926.

[5] ALI A M A, MORGAN A, DILLON C, et al. A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration ［J］. IEEE J Sol Sta Circ, 2010, 45(12): 2602-2612.

[7] SONG B S, TOMPSETT M F, LAKSHMIKUMAR K R. A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter ［J］. IEEE J Sol Sta Circ, 1988, 23(6): 1324-1333.

[8] ALI A M A, DINC H, BHORASKAR P, et al. A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration ［J］. IEEE J Sol Sta Circ, 2014, 49(12): 2857-2867.

[10] HELFENSTEIN M. CMOS data converters for communications ［Book Reviews］［J］. IEEE Circuits and Devices Magazine, 2000, 16(4): 39-40.

[12] ROY S, BASAK H, BANERJEE S. Foreground calibration technique of a pipeline ADC using capacitor ratio of multiplying digital-to-analog converter (MDAC) ［J］. Microelec J, 2013, 44(12): 1336-1347.