A foreground digital calibration technology for pipelined ADC was introduced. The calibration was mainly aimed at the sampling capacitor mismatch in MDAC, which increased the nonlinearity of ADC output. The proposed foreground digital calibration technology used the relative deviation of the integral nonlinearity of the ADC output to extract the error, and used a simple multi-channel selection operation unit to compensate the error. On this basis, Verilog HDL was used to realize RTL level description, and the circuit was taped out successfully. Simulation and test results showed that the proposed calibration algorithm could improve the output performance of ADC.