Author Affiliations
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts andTelecommunications, Nanjing , Jiangsu 210023, Chinashow less
Fig. 1. Energy band diagram of complete photonic crystal structure
Fig. 2. Structure diagram of half-adder based on AND and XOR logic gates
Fig. 3. TE mode steady-state field distribution of half-adder. (a) A∶0, B∶1; (b) A∶1, B∶0; (c) A∶B∶1
Fig. 4. Time-domain steady state response diagrams of half-adder. (a) A∶0, B∶1; (b) A∶1, B∶0; (c) A∶B∶1
Fig. 5. Structure diagram of the optimized half-adder
Fig. 6. TE mode steady-state field distribution of structure-optimized half-adder. (a) A∶0, B∶1; (b) A∶1, B∶0; (c) A∶B∶1
Fig. 7. Time-domain steady state response diagrams of structure-optimized half-adder. (a) A∶0, B∶1; (b) A∶1, B∶0; (c) A∶B∶1
Input A | | Input B | | Output C | | Output S |
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Logic level | Power | Logic level | Power | Logic level | Normalized Power | Logic level | Normalized Power | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Pin | 0 | 0.142 | 1 | 0.663 | 1 | Pin | 0 | 0 | 0 | 0.125 | 1 | 0.418 | 1 | Pin | 1 | Pin | 1 | 0.417 | 0 | 0.035 |
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Table 1. Performance accuracy table and the output power levels of the half-adder designed
Input A | | Input B | | Output C | | Output S |
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Logic level | Power | Logic level | Power | Logic level | Normalized Power | Logic level | Normalized Power | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Pin | 0 | 0.109 | 1 | 0.605 | 1 | Pin | 0 | 0 | 0 | 0.136 | 1 | 0.465 | 1 | Pin | 1 | Pin | 1 | 0.911 | 0 | 0.0136 |
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Table 2. Performance accuracy table and the output power levels of structure-optimized half-adder