• Microelectronics
  • Vol. 51, Issue 5, 666 (2021)
ZHAO Wenbin, ZHANG Changchun, ZHANG Guanghua, and DONG Shulu
Author Affiliations
  • [in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.200569 Cite this Article
    ZHAO Wenbin, ZHANG Changchun, ZHANG Guanghua, DONG Shulu. A 25 Gbit/s CMOS Adaptive Decision Feedback Equalizer[J]. Microelectronics, 2021, 51(5): 666 Copy Citation Text show less
    References

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    [2] GARG A, CARUSONE A C, VOINIGESCU S P. A 1-tap 40 Gb/s look-ahead decision feedback equalizer in 0.18 μm SiGe BiCMOS technology [J]. IEEE J Sol Sta Circ, 2006, 41(10): 2224-2232.

    [3] SOHN Y S, BAE S J, PARK H J, et al. A 1.2 Gb/s CMOS DFE receiver with the extended sampling time window for application to the SSTL channel [C]//Symp VLSI Circ Dig Tech Pap. Honolulu, HI, USA. 2002: 92-93.

    [4] IBRAHIM S, RAZAVI B. Low power CMOS equalizer design for 20Gb/s systems [J]. IEEE J Sol Sta Circ, 2011, 46(6): 1321-1336.

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    [7] COHEN S, FAIG H, GANTZ L, et al. Robust dithering based stabilization for quantized LMS adaptation [C]//45th Euro Conf Opt Commun. Dublin, Ireland. 2019: 1-4.

    [8] WU X, HU Q S. Design of a 6.25Gb/s adaptive decision feedback equalizer in 0.18 μm CMOS technology [C]//IEEE WARTIA. Ottawa, Canada. 2014: 1209-1212.

    [10] VAMVAKOS S D, BOECKER C, GROEN E, et al. A 8.125-15.625 Gb/s SerDes using a sub-sampling ring oscillator phase-locked loop [C]//Custom Integr Circ Conf. San Jose, CA, USA. 2014: 1-4.

    [11] SINGH U, GARG A, RAGHAVAN B, et al. A 780 mW 4×28 Gb/s transceiver for 100 GbE gearbox PHY in 40 nm CMOS [C]//IEEE ISSCC. San Francisco, CA, USA. 2014: 40-41.

    CLP Journals

    [1] JIN Gaozhe, ZHANG Changchun, YUAN Feng, ZHANG Ying, ZHANG Yi. Design of a 25-28 Gbit/s CMOS High Sensitive Optical Receiver[J]. Microelectronics, 2023, 53(4): 581

    ZHAO Wenbin, ZHANG Changchun, ZHANG Guanghua, DONG Shulu. A 25 Gbit/s CMOS Adaptive Decision Feedback Equalizer[J]. Microelectronics, 2021, 51(5): 666
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