• Microelectronics
  • Vol. 52, Issue 1, 77 (2022)
SUN Haonan, WANG Junchao, LI Haoliang, and ZHANG Yingtao
Author Affiliations
  • [in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.210103 Cite this Article
    SUN Haonan, WANG Junchao, LI Haoliang, ZHANG Yingtao. A Novel Latch-Immune LDMOS for High-Voltage Protection[J]. Microelectronics, 2022, 52(1): 77 Copy Citation Text show less
    References

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    [3] CHEN W Y, KER M D. New layout arrangement to improve ESD robustness of large-array high-voltage nLDMOS [J]. IEEE Elec Dev Lett, 2010, 31(2): 159-161.

    [7] LIU Z, SONG W Q, HOU F, et al. Improved LDMOS-SCR for high-voltage electrostatic discharge (ESD) protection applications [J]. Elec Lett, 2020, 56(13): 680-682.

    [8] JIN X L, WANG Y, ZHONG Z Y. Optimization of LDMOS-SCR device for ESD protection based on 0.5 μm CMOS process [C] // 12th EMC Compo. Hangzhou, China. 2019.

    [9] FAN H, JIANG L, ZHANG B. A method to prevent strong snapback in LDNMOS for ESD protection [J]. IEEE Trans Dev Mater Reliab, 2013, 13(1): 50-53.

    [10] YE R, LIU S Y, DAI Z G, et al. ESD failure analysis and robustness improvement for multi-STI-finger LDMOS used as output device [C] // IEEE 30th ISPSD. Chicago, IL, USA. 2018: 339-342.

    SUN Haonan, WANG Junchao, LI Haoliang, ZHANG Yingtao. A Novel Latch-Immune LDMOS for High-Voltage Protection[J]. Microelectronics, 2022, 52(1): 77
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