• Journal of Inorganic Materials
  • Vol. 38, Issue 4, 445 (2023)
Jingyu WANG1, Changjin WAN1, and Qing WAN1,2,*
Author Affiliations
  • 11. School of Electronic Science and Engineering, Nanjing University, Nanjing 210093, China
  • 22. School of Micro-Nano Electronics, Zhejiang University, Hangzhou 310027, China
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    DOI: 10.15541/jim20220767 Cite this Article
    Jingyu WANG, Changjin WAN, Qing WAN. Dual-gate IGZO-based Neuromorphic Transistors with Stacked Al2O3/Chitosan Gate Dielectrics [J]. Journal of Inorganic Materials, 2023, 38(4): 445 Copy Citation Text show less
    Schematic diagram of the IGZO-based neuromorphic transistor with different gate dielectrics
    1. Schematic diagram of the IGZO-based neuromorphic transistor with different gate dielectrics
    Leakage current curves and corresponding AFM images (inset) of monolayer gate dielectric and bilayer gate dielectric
    2. Leakage current curves and corresponding AFM images (inset) of monolayer gate dielectric and bilayer gate dielectric
    Transfer characteristics and output characteristics of two kinds of dielectric devices
    3. Transfer characteristics and output characteristics of two kinds of dielectric devices
    (a) Top micrograph, (b) transfer characteristics with different VG2 (from-2.0 V to 1.0 V) and (c) the Vth with different VG2 of transistor
    4. (a) Top micrograph, (b) transfer characteristics with different VG2 (from-2.0 V to 1.0 V) and (c) the Vth with different VG2 of transistor
    (a) Schematic diagram of biological synapse and their equivalent electrical circuit of the neuromorphic transistor, (b) EPSC responses under an electric pulse of 0.5 V, and (c) EPSC induced by electric pulses of different amplitudes for IGZO-based dual-gate transistor with stacked Al2O3/chitosan gate dielectrics
    5. (a) Schematic diagram of biological synapse and their equivalent electrical circuit of the neuromorphic transistor, (b) EPSC responses under an electric pulse of 0.5 V, and (c) EPSC induced by electric pulses of different amplitudes for IGZO-based dual-gate transistor with stacked Al2O3/chitosan gate dielectrics
    (a) Multi-pulse facilitation induced by eight successive electric pulse (0.5 V, 25 ms) and (b) ratio of A8/A1 plotted as a function of the time interval between the pulses for IGZO-based dual-gate transistor with stacked Al2O3/chitosan gate dielectrics
    6. (a) Multi-pulse facilitation induced by eight successive electric pulse (0.5 V, 25 ms) and (b) ratio of A8/A1 plotted as a function of the time interval between the pulses for IGZO-based dual-gate transistor with stacked Al2O3/chitosan gate dielectrics
    Gate dielectricIoffIon/Ioff ratio Subthreshold swing/ (mV·decade-1) Hysteresis window/V Leakage current(VG=1.8 V)/nA μsat/(cm2·V-1·s-1)
    Chitosan2.92×10-91.06×10598.81.1066.418.0
    Chitosan/Al2O34.20×10-112.20×10678.33.731.320.9
    Table 1. Transistor parameters of IGZO-based transistors
    StructureVDS/V VG pulse EPSC/nAEnergy consumption/(pJ·spike-1) Ref.
    Nanogranular SiO2/IZO1.00.8 V, 20 ms5000105[33]
    GO+Chitosan/IGZO0.10.5 V, 20 ms1428[34]
    Carbon Nanotube (CNT)0.54.0 V, 1.0 ms157.5[35]
    Chitosan/IZO0.10.5 V, 25 ms2.66.5[36]
    Chitosan/IWO0.10.2 V, 20 ms4.79.4[37]
    Chitosan/IGZO0.10.5 V, 20 ms2652[38]
    Tungsten oxide0.30.6 V, 70 ms3.879[39]
    Chitosan/ IGZO0.10.5 V, 20 ms2448This work
    Chitosan/Al2O3/IGZO0.10.5 V, 20 ms0.861.7This work
    Table 2. Energy consumption of the single EPSC peak in different artificial synaptic transistors
    Jingyu WANG, Changjin WAN, Qing WAN. Dual-gate IGZO-based Neuromorphic Transistors with Stacked Al2O3/Chitosan Gate Dielectrics [J]. Journal of Inorganic Materials, 2023, 38(4): 445
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