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Journals >Journal of Semiconductors >Volume 44 >Issue 5 >Page 050205 > Article

Journal of Semiconductors
Vol. 44, Issue 5, 050205 (2023)

CMOS phase-locked loops in ISSCC 2023

Zhao Zhang^1,2,*

Author Affiliations

¹State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

²Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

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DOI: 10.1088/1674-4926/44/5/050205 Cite this Article

Zhao Zhang. CMOS phase-locked loops in ISSCC 2023[J]. Journal of Semiconductors, 2023, 44(5): 050205 Copy Citation Text

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References

[1] P T Renukaswamy, K Vaesen, N Markulic et al. A 16GHz, 41kHzrms frequency error, background-calibrated, duty-cycled FMCW charge-pump PLL. IEEE International Solid-State Circuit Conference, 68(2023).

[2] Y Jo, J Kim, Y Shin et al. A 135fsrms-jitter 0.6-to-7.7GHz LO generator using a single LC-VCO-based subsampling PLL and a ring-oscillator-based sub-integer-N frequency multiplier. IEEE International Solid-State Circuit Conference, 71(2023).

[3] S M Dartizio1, F Tesolin, G Castoro1 et al. A 76.7fs-integrated-jitter and -71.9dBc in-band fractional-spur bang-bang digital PLL based on an inverse-constant-slope DTC and FCW subtractive dithering. IEEE International Solid-State Circuit Conference, 74(2023).

[4] J Qiu, W Wang, Z Sun et al. A 32kHz-reference 2.4GHz fractional-N nonuniform oversampling PLL with gain-boosted PD and loop-gain calibration. IEEE International Solid-State Circuit Conference, 77(2023).

[5] G Castoro, S M Dartizio, F Tesolin et al. A 9.25GHz digital PLL with fractional-spur cancellation based on a multi-DTC topology. IEEE International Solid-State Circuit Conference, 80(2023).

[6] J Bang, J Kim, S Jung et al. A 47fsrms-jitter and 26.6mW 103.5GHz PLL with power-gating injection-locked frequency-multiplier-based phase detector and extended loop bandwidth. IEEE International Solid-State Circuit Conference, 83(2023).

[7] Z Zhang, X Shen, Z Zhang et al. A 0.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL achieving 236.6fsrms jitter, -253.8dB jitter-power FoM, and -76.1dBc reference spur. IEEE International Solid-State Circuit Conference, 86(2023).

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Zhao Zhang. CMOS phase-locked loops in ISSCC 2023[J]. Journal of Semiconductors, 2023, 44(5): 050205

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