4H-silicon carbide (4H-SiC) MOSFETs are attractive for converters and inverters which require fast switching speed and low specific R_{on, sp}, owing to superior properties of SiC material and unipolar operation mechanism of MOSFETs^[1–4]. SiC trench MOSFETs have high MOS-channel density and high channel mobility on trench sidewalls^[5–10]. However, the trench corner suffers from a high electric field in the gate oxide in the blocking mode, which significantly influences the BV value and device reliability. In order to relieve the electric field in the gate oxide, the conventional trench MOSFET (CT-MOS) adopts a PSR under the trench gate^[11–16], the double-trench MOSFET (DT-MOS) introduces a PSR to constitute a trench source^[17]. Meanwhile, the PSR could also reduce Q_GD, which improves the switching behavior. To further reduce Q_GD and make the SiC trench MOSFETs more suitable for the application towards high frequency, efforts must be made to decrease the Q_GD and improve the dynamic characteristics of SiC trench MOSFETs.

In this paper, a novel trench MOSFET with double shielding structures (DS-MOS) is proposed. Sentaurus TCAD simulation demonstrates that the DS-MOS shows ultralow C_GD and Q_GD. Moreover, the switching loss of the DS-MOS, CT-MOS and DT-MOS is also discussed in this paper.

Fig. 1(a) shows the schematic structure of the proposed DS-MOS. It features a grounded SG and a trench PSR. The PSR surrounds the trench source and the SG is below the trench control gate. T_ox is the distance from the SG to the oxide bottom of trench, and L_ox is the distance from the SG to the sidewall of oxide trench. Figs. 1(b) and 1(c) show the schematic structures of the DT-MOS and CT-MOS, respectively. For DS-MOS and the DT-MOS, L_s represents the length of P-base region. For CT-MOS, L stands for the lateral space between the PSR and the gate oxide boundary. The doping concentration and thickness of the drift region are 6 × 10¹⁵ cm^–3 and 10 μm, respectively. The other parameters are shown in Table 1.

Fig. 2 illustrates the operation mechanism of double shielding structures. The structure in Fig. 2(a) is the trench gate MOSFET without the SG and the PSR^[18]. The structure in Fig. 2(b)^{[18, 19]} is the split gate MOSFET with the SG and the structure in Fig. 2(c) is the DT-MOS with the PSR. The DS-MOS has both SG and the PSR as shown in Fig. 2(d). On one hand, the SG acts as a shielding region between the gate and drain, and transforms part of the C_GD into the C_DS1 and C_GS1 in series, as illustrated in Fig. 2(b), the C_GD of split trench gate MOSFET can be demonstrated as: C_GD = (C_GS1^–1 + C_DS1^–1)^–1 + C_GD3. On the other hand, the PSR reduces the C_GD by partially transforming the C_GD to C_GS2 and C_DS2 in series, as illustrated in Fig. 2(c), the C_GD of DT-MOS can be demonstrated as: C_GD = (C_DS2^–1 + C_GS2^–1)^–1 + C_GD4. Under combination of the SG and PSR, the C_GD of DS-MOS can be demonstrated as: C_GD = (C_GS3^–1 + C_DS3^–1)^–1 + C_GD5 + (C_GS4^–1 + C_DS4^–1)^–1, as shown in Fig. 2(d). Under the same structure parameters, Fig. 3 compares the simulation results of C_GD of the four structures shown in Fig. 2. The results verify the significant improvement of the double shielding structures on C_GD. It is obvious that the C_GD of the trench MOSFETs with only one shielding structure (Fig. 2(b) and Fig. 2(c)) are smaller than that of the trench MOSFET without shielding structures (Fig. 2(a)). More importantly, the proposed DS-MOS obtains the lowest C_GD owing to the interacting shielding effect induced by the double shielding structures.

In order to ensure good static characteristics of DS-MOS, T_ox and L_ox should be optimized. In this paper, the breakdown voltage (BV) is defined as the drain voltage at which either the impact ionization integral equals to unity or the electric field in the gate oxide reaches 3 MV/cm, and R_{on, sp} is estimated at V_GS = 20 V and V_DS = 1 V. The channel mobility is set as 15 cm²/(V·s). Figs. 4(a)–4(c) show the influence of L_s, T_ox and L_ox on BV, R_{on, sp} and FOM (BV²/R_{on, sp}) for the DS-MOS. With the increase in L_s, the BV of DS-MOS decreases because the shielding effect of the PSR on gate oxide is weakened and thus the gate oxide breakdown is more likely to occur. In addition, larger L_s widens the current flow path and leads to lower R_{on, sp}. Therefore, to obtain a desirable trade-off between BV and R_{on, sp}, ie, the highest FOM = BV²/R_{on, sp} value, the optimum L_s = 1.1 μm is chosen. Fig. 4(d) depicts the influences of the T_ox and L_ox on the electron density. In the on state, the SG, oxide and N-drift form the MIS structures (marked by the black dotted line in Fig. 4(d)). The MIS structure forms depletion regions in the drift region (the depletion region boundaries are marked by the white line), and then JFET resistance is generated. High L_ox and T_ox values will weaken the lateral depletion effect of the MIS structure and maintain wide electron current path, which contributes to a low R_{on, sp}. Therefore, the optimized L_ox is 0.3 μm. Under the optimized L_s and L_ox, T_ox will also affect the length of the accumulation channel (marked by the two-way arrow). Considering the BV of DS-MOS, the optimized T_ox and L_ox are 0.2 and 0.3 μm, respectively. In conclusion, the optimized R_{on, sp} is 4.08 mΩ·cm² (denoted as point “A”) and BV is 1435 V (denoted as point “B”) in Fig. 4(b).

Fig. 5 shows the dependences of C_GD on L_s, T_ox and L_ox for DS-MOS. The C_GD slowly increases with the increase in T_ox, the reason is that the shielding effect is weakened if the distance between the SG and controlled gate electrode shortens. For L_s, the increasing L_s weakens the shielding effect of the PSR against the gate–drain coupling, thus the C_GD increases. Obviously, the C_GD is more sensitive to L_ox than T_ox at the same L_s, which means reducing the overlap of the gate–drain is more important than the location of the SG. Owing to the weakened shielding effect of the PSR on C_GD with the increase in L_s, the influence of the L_ox on C_GD becomes more important.

Fig. 6 shows the on-state output characteristic curves of the DS-MOS, DT-MOS and CT-MOS. To obtain the highest FOM (BV²/R_{on, sp}), the optimized values of L_s = 0.9 μm and L = 0.3 μm are chosen for the DT-MOS and CT-MOS. The R_{on, sp} values of DS-MOS, DT-MOS and CT-MOS are 4.08, 3.72 and 3.96 mΩ·cm², respectively. The R_{on, sp} of the proposed device is a little bit higher than the other devices because of the JFET resistance generated by the SG and PSR, as shown in Fig. 4(d). With the increase in V_DS, the JFET resistance increases and then the DS-MOS shows the lowest saturation current. Therefore, the DS-MOS is constructive to improve the short circuit capability of the device.

Fig. 7 compares the C_GD and Q_GD of the DS-MOS, DT-MOS and CT-MOS. Owing to the shielding effect of the SG and PSR, the DS-MOS has the lowest C_GD compared with other two devices. The C_GD (@V_DS = 600 V) of the DS-MOS, DT-MOS and CT-MOS are 13, 68 and 83 pF/cm², respectively. The DS-MOS exhibits the shortest Miller platform and smallest Q_GD of 26 nC/cm² compared with the DT-MOS and CT-MOS, as shown in Fig. 7(b). Compared with the DT-MOS and CT-MOS, the Q_GD of DS-MOS is reduced by 85% and 81%, respectively.

Fig. 8 shows the tradeoff between R_{on, sp} and Q_GD for the DS-MOS, DT-MOS and CT-MOS. A large L_s and L can reduce the JFET resistance and the R_{on, sp}. For the DS-MOS and the DT-MOS, the effect is weakened as L_s and L increase. The increase in L_s results in an increase in C_GD and Q_GD because the shielding effect is weakened. The higher L directly causes a larger overlap area between the gate electrode and the drain electrode for the CT-MOS, and thus higher C_GD and Q_GD are obtained. What’s more, the protection on gate oxide caused by the PSR becomes weak. Under the almost same R_{on, sp}, the Q_GD of the DS-MOS is reduced by 85% and 81% compared with that of DT-MOS and CT-MOS, respectively.

Figs. 9(a) and 9(b) show the turn-off waveforms and simulation circuit of the three MOSFETs. The MOSFETs turn off at t = 20 μs and the devices are all 1 cm². A SiC junction barrier Schottky diode (JBS) is used as the freewheeling diode and the gate resistor (R_G) is set as 20 Ω. Owing to ultralow Q_GD for the DS-MOS, the high dV/dt and dI/dt values are obtained, leading to 76% and 80% reduction in turn-off losses (E_off) compared with that of the DTMOS and CT-MOS, respectively. The specific dV/dt and dI/dt of the three MOSFETs are shown in Table 2.

Fig. 10(a) shows the influence of the R_G on switching loss (E_on + E_off) in one switching cycle. Compared with the DT-MOS and the CT-MOS, the DS-MOS exhibits the lowest switching loss at different R_G. As the R_G increases, the difference of the switching loss among the three MOSFETs increases. The total power losses P_t of the device consist of conduction losses and switching losses, and can be calculated using^{[20, 21]}:

$ {P_{\rm t}} = {\rm d} {R_{\rm on,sp}} {I_{\rm d}}^2 + f ({E_{\rm on}} + {E_{\rm off}}), $  ()

where d stands for the duty cycle which defined as the ratio of the time the MOSFET conducts to a switching period, and f is the switching frequency. Fig. 10(b) shows the power losses as a function of switching frequency and the duty cycle is set as 0.5. With the increasing switching frequency, switching losses become the dominant power dissipation and the advantage of switching performance of DS-MOS increases. When operating at 200 kHz, the DS-MOS realizes 48% and 43% reduction in the power losses compared with the DT-MOS and the CT-MOS. Table 2 summarizes the performance parameters for the three devices. Obviously, the DS-MOS obtains better performance than other two MOSFETs.

Fig. 11(a) shows the 3-D view of DS-MOS. The SG is grounded through the contact holes along the z axis and the schematic cross section along the cut line AA’ is shown in Fig. 11(b). To avoid the electric connection between the gate and SG, there is a dielectric layer between them.

A novel 4H-SiC trench MOSFET with double shielding structures is proposed in this paper. The double shielding structures include a split gate and a trench P⁺ shielding region. The Q_GD of the proposed DS-MOS reduced by 85% and 81% compared with that of DT-MOS and CT-MOS without sacrificing BV, leading to a significantly improvement in the switching performance. Furthermore, the FOM defined as R_{on, sp}Q_GD of the DS-MOS is decreased by 84% and 81% in comparison with that of the DT-MOS and CT-MOS, respectively, and thus the power dissipation is reduced, which makes the DS-MOS suitable for the high frequency and high power applications.

This work was supported by the National Key Research and Development Program of China (No. 2016YFB0400502).