Abstract
1. Introduction
4H-silicon carbide (4H-SiC) MOSFETs are attractive for converters and inverters which require fast switching speed and low specific Ron, sp, owing to superior properties of SiC material and unipolar operation mechanism of MOSFETs[
In this paper, a novel trench MOSFET with double shielding structures (DS-MOS) is proposed. Sentaurus TCAD simulation demonstrates that the DS-MOS shows ultralow CGD and QGD. Moreover, the switching loss of the DS-MOS, CT-MOS and DT-MOS is also discussed in this paper.
2. Device structure and mechanism
Fig. 1(a) shows the schematic structure of the proposed DS-MOS. It features a grounded SG and a trench PSR. The PSR surrounds the trench source and the SG is below the trench control gate. Tox is the distance from the SG to the oxide bottom of trench, and Lox is the distance from the SG to the sidewall of oxide trench. Figs. 1(b) and 1(c) show the schematic structures of the DT-MOS and CT-MOS, respectively. For DS-MOS and the DT-MOS, Ls represents the length of P-base region. For CT-MOS, L stands for the lateral space between the PSR and the gate oxide boundary. The doping concentration and thickness of the drift region are 6 × 1015 cm–3 and 10 μm, respectively. The other parameters are shown in Table 1.
Figure 1.(Color online) Schematic cross section of the (a) proposed DS-MOS, (b) DT-MOS, and (c) CT-MOS.
Table Infomation Is Not EnableFig. 2 illustrates the operation mechanism of double shielding structures. The structure in Fig. 2(a) is the trench gate MOSFET without the SG and the PSR[
Figure 2.(Color online) Capacitance distribution for (a) trench gate MOSFET without SG & PSR, (b) split trench gate MOSFET with SG, (c) DT-MOS, and (d) DS-MOS.
Figure 3.(Color online)
3. Results and discussion
In order to ensure good static characteristics of DS-MOS, Tox and Lox should be optimized. In this paper, the breakdown voltage (BV) is defined as the drain voltage at which either the impact ionization integral equals to unity or the electric field in the gate oxide reaches 3 MV/cm, and Ron, sp is estimated at VGS = 20 V and VDS = 1 V. The channel mobility is set as 15 cm2/(V·s). Figs. 4(a)–4(c) show the influence of Ls, Tox and Lox on BV, Ron, sp and FOM (BV2/Ron, sp) for the DS-MOS. With the increase in Ls, the BV of DS-MOS decreases because the shielding effect of the PSR on gate oxide is weakened and thus the gate oxide breakdown is more likely to occur. In addition, larger Ls widens the current flow path and leads to lower Ron, sp. Therefore, to obtain a desirable trade-off between BV and Ron, sp, ie, the highest FOM = BV2/Ron, sp value, the optimum Ls = 1.1 μm is chosen. Fig. 4(d) depicts the influences of the Tox and Lox on the electron density. In the on state, the SG, oxide and N-drift form the MIS structures (marked by the black dotted line in Fig. 4(d)). The MIS structure forms depletion regions in the drift region (the depletion region boundaries are marked by the white line), and then JFET resistance is generated. High Lox and Tox values will weaken the lateral depletion effect of the MIS structure and maintain wide electron current path, which contributes to a low Ron, sp. Therefore, the optimized Lox is 0.3 μm. Under the optimized Ls and Lox, Tox will also affect the length of the accumulation channel (marked by the two-way arrow). Considering the BV of DS-MOS, the optimized Tox and Lox are 0.2 and 0.3 μm, respectively. In conclusion, the optimized Ron, sp is 4.08 mΩ·cm2 (denoted as point “A”) and BV is 1435 V (denoted as point “B”) in Fig. 4(b).
Figure 4.(Color online) Tradeoff between
Fig. 5 shows the dependences of CGD on Ls, Tox and Lox for DS-MOS. The CGD slowly increases with the increase in Tox, the reason is that the shielding effect is weakened if the distance between the SG and controlled gate electrode shortens. For Ls, the increasing Ls weakens the shielding effect of the PSR against the gate–drain coupling, thus the CGD increases. Obviously, the CGD is more sensitive to Lox than Tox at the same Ls, which means reducing the overlap of the gate–drain is more important than the location of the SG. Owing to the weakened shielding effect of the PSR on CGD with the increase in Ls, the influence of the Lox on CGD becomes more important.
Figure 5.(Color online) Dependence of
Fig. 6 shows the on-state output characteristic curves of the DS-MOS, DT-MOS and CT-MOS. To obtain the highest FOM (BV2/Ron, sp), the optimized values of Ls = 0.9 μm and L = 0.3 μm are chosen for the DT-MOS and CT-MOS. The Ron, sp values of DS-MOS, DT-MOS and CT-MOS are 4.08, 3.72 and 3.96 mΩ·cm2, respectively. The Ron, sp of the proposed device is a little bit higher than the other devices because of the JFET resistance generated by the SG and PSR, as shown in Fig. 4(d). With the increase in VDS, the JFET resistance increases and then the DS-MOS shows the lowest saturation current. Therefore, the DS-MOS is constructive to improve the short circuit capability of the device.
Figure 6.(Color online) On-state output characteristic curves of the three devices at
Fig. 7 compares the CGD and QGD of the DS-MOS, DT-MOS and CT-MOS. Owing to the shielding effect of the SG and PSR, the DS-MOS has the lowest CGD compared with other two devices. The CGD (@VDS = 600 V) of the DS-MOS, DT-MOS and CT-MOS are 13, 68 and 83 pF/cm2, respectively. The DS-MOS exhibits the shortest Miller platform and smallest QGD of 26 nC/cm2 compared with the DT-MOS and CT-MOS, as shown in Fig. 7(b). Compared with the DT-MOS and CT-MOS, the QGD of DS-MOS is reduced by 85% and 81%, respectively.
Figure 7.(Color online) Comparison of (a)
Fig. 8 shows the tradeoff between Ron, sp and QGD for the DS-MOS, DT-MOS and CT-MOS. A large Ls and L can reduce the JFET resistance and the Ron, sp. For the DS-MOS and the DT-MOS, the effect is weakened as Ls and L increase. The increase in Ls results in an increase in CGD and QGD because the shielding effect is weakened. The higher L directly causes a larger overlap area between the gate electrode and the drain electrode for the CT-MOS, and thus higher CGD and QGD are obtained. What’s more, the protection on gate oxide caused by the PSR becomes weak. Under the almost same Ron, sp, the QGD of the DS-MOS is reduced by 85% and 81% compared with that of DT-MOS and CT-MOS, respectively.
Figure 8.(Color online) Tradeoff between
Figs. 9(a) and 9(b) show the turn-off waveforms and simulation circuit of the three MOSFETs. The MOSFETs turn off at t = 20 μs and the devices are all 1 cm2. A SiC junction barrier Schottky diode (JBS) is used as the freewheeling diode and the gate resistor (RG) is set as 20 Ω. Owing to ultralow QGD for the DS-MOS, the high dV/dt and dI/dt values are obtained, leading to 76% and 80% reduction in turn-off losses (Eoff) compared with that of the DTMOS and CT-MOS, respectively. The specific dV/dt and dI/dt of the three MOSFETs are shown in Table 2.
Figure 9.(Color online) (a) Turn-off waveforms of the DS-MOS, DT-MOS and CT-MOS, respectively. (b) Simulation circuit of the turn-off characteristics.
Table Infomation Is Not EnableFig. 10(a) shows the influence of the RG on switching loss (Eon + Eoff) in one switching cycle. Compared with the DT-MOS and the CT-MOS, the DS-MOS exhibits the lowest switching loss at different RG. As the RG increases, the difference of the switching loss among the three MOSFETs increases. The total power losses Pt of the device consist of conduction losses and switching losses, and can be calculated using[
Figure 10.(Color online) (a) Dependence of
where d stands for the duty cycle which defined as the ratio of the time the MOSFET conducts to a switching period, and f is the switching frequency. Fig. 10(b) shows the power losses as a function of switching frequency and the duty cycle is set as 0.5. With the increasing switching frequency, switching losses become the dominant power dissipation and the advantage of switching performance of DS-MOS increases. When operating at 200 kHz, the DS-MOS realizes 48% and 43% reduction in the power losses compared with the DT-MOS and the CT-MOS. Table 2 summarizes the performance parameters for the three devices. Obviously, the DS-MOS obtains better performance than other two MOSFETs.
Fig. 11(a) shows the 3-D view of DS-MOS. The SG is grounded through the contact holes along the z axis and the schematic cross section along the cut line AA’ is shown in Fig. 11(b). To avoid the electric connection between the gate and SG, there is a dielectric layer between them.
Figure 11.(a) 3-D view of DS-MOS. (b) Schematic cross section along the cut line AA’.
4. Conclusion
A novel 4H-SiC trench MOSFET with double shielding structures is proposed in this paper. The double shielding structures include a split gate and a trench P+ shielding region. The QGD of the proposed DS-MOS reduced by 85% and 81% compared with that of DT-MOS and CT-MOS without sacrificing BV, leading to a significantly improvement in the switching performance. Furthermore, the FOM defined as Ron, spQGD of the DS-MOS is decreased by 84% and 81% in comparison with that of the DT-MOS and CT-MOS, respectively, and thus the power dissipation is reduced, which makes the DS-MOS suitable for the high frequency and high power applications.
Acknowledgements
This work was supported by the National Key Research and Development Program of China (No. 2016YFB0400502).
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