The architecture of the multilevel filter ASIC chip used for image processing is described.There are one input FIFO and three output FIFO controlled by the control module to realize multiplex image data real time processing and transferring efficiently. Considering FIFOs′ design and application in the chip, one asynchronous FIFO buffers and stores input data to match datapath to slower data import; three synchronous FIFOs are designed separately as buffer storages of image processing data from three level filter ,whose templates are separately 1×3?1×5(equates to the cascade connection of two 1×3 templates)and 1×7(equates to the cascade connection of three 1×3 templates).The three FIFOs occupy an output data bus by the way of time-sharing.Simulation results indicate that the design is right and effective.