• Journal of Semiconductors
  • Vol. 42, Issue 8, 082401 (2021)
Qiao Wang1、2, Donglin Zhang1、2, Yulin Zhao1、2, Chao Liu1, Xiaoxin Xu1、2, Jianguo Yang1、3, and Hangbing Lv1、2
Author Affiliations
  • 1Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
  • 2University of Chinese Academy of Sciences, Beijing 100049, China
  • 3Zhejiang Lab, Hangzhou 311121, China
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    DOI: 10.1088/1674-4926/42/8/082401 Cite this Article
    Qiao Wang, Donglin Zhang, Yulin Zhao, Chao Liu, Xiaoxin Xu, Jianguo Yang, Hangbing Lv. Low-cost dual-stage offset-cancelled sense amplifier with hybrid read reference generator for improved read performance of RRAM at advanced technology nodes[J]. Journal of Semiconductors, 2021, 42(8): 082401 Copy Citation Text show less
    References

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    [2] J Woo, S M Yu. Two-step read scheme in one-selector and one-RRAM crossbar-based neural network for improved inference robustness. IEEE Trans Electron Devices, 65, 5549(2018).

    [3] M F Chang, C W Wu, C C Kuo et al. A 0.5 V 4 Mb logic-process compatible embedded resistive RAM (ReRAM) in 65 nm CMOS using low-voltage current-mode sensing scheme with 45 ns random read time. 2012 IEEE International Solid-State Circuits Conference, 434(2012).

    [4] P Jain, U Arslan, M Sekhar et al. 13.2 A 3.6 Mb 10.1Mb/mm2 embedded non-volatile ReRAM macro in 22 nm FinFET technology with adaptive forming/set/reset schemes yielding down to 0.5 V with sensing time of 5 ns at 0.7 V. 2019 IEEE International Solid-State Circuits Conference, 212(2019).

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    [7] T Na, B Song, J P Kim et al. Offset-canceling current-sampling sense amplifier for resistive nonvolatile memory in 65 nm CMOS. IEEE J Solid-State Circuits, 52, 496(2017).

    [8] Q Dong, Z H Wang, J Lim et al. A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in situ self-write-termination. IEEE International Solid-State Circuits Conference, 480(2018).

    [9] M F Chang, S J Shen, C C Liu et al. An offset-tolerant current-sampling-based sense amplifier for sub-100nA-cell-current nonvolatile memory. IEEE International Solid-State Circuits Conference, 206(2011).

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    [15] M F Chang, S S Sheu, K F Lin et al. A high-speed 7.2-ns read-write random access 4-mb embedded resistive RAM (ReRAM) macro using process-variation-tolerant current-mode read schemes. IEEE J Solid-State Circuits, 48, 878(2013).

    [16] Q K Trinh, S Ruocco, M Alioto. Dynamic reference voltage sensing scheme for read margin improvement in STT-MRAMs. IEEE Trans Circuits Syst I, 65, 1269(2018).

    [17] W Kang, T T Pang, W Lv et al. Dynamic dual-reference sensing scheme for deep submicrometer STT-MRAM. IEEE Trans Circuits Syst I, 64, 122(2017).

    [18] Y L Zhou, H Cai, L Xie et al. A self-timed voltage-mode sensing scheme with successive sensing and checking for STT-MRAM. IEEE Trans Circuits Syst I, 67, 1602(2020).

    Qiao Wang, Donglin Zhang, Yulin Zhao, Chao Liu, Xiaoxin Xu, Jianguo Yang, Hangbing Lv. Low-cost dual-stage offset-cancelled sense amplifier with hybrid read reference generator for improved read performance of RRAM at advanced technology nodes[J]. Journal of Semiconductors, 2021, 42(8): 082401
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