• Microelectronics
  • Vol. 52, Issue 4, 603 (2022)
LI Xiao1, LI Xiaoran2, ZHANG Hao2, YANG Jiaheng2, and ZHANG Lei2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.210462 Cite this Article
    LI Xiao, LI Xiaoran, ZHANG Hao, YANG Jiaheng, ZHANG Lei. Design of a 10-bit High Speed Pipeline-SAR Hybrid ADC[J]. Microelectronics, 2022, 52(4): 603 Copy Citation Text show less
    References

    [1] MULDER A J, JOHNS D A. A 50 MS/s 9.9 mW pipeline ADC with 58 dB SNDR in 0.18 μm CMOS using capacitive charge pumps [C]// IEEE ISSCC. San Francisco, CA, USA. 2009: 164-165.

    [3] GANDARA M, GULATI P, SUN N. A 172 dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration [C]// IEEE A-SSCC. Seoul, South Korea. 2017: 297-300.

    [4] IMANI A, BAKHTIAR M S. A two-stage pipelined passive charge-sharing SAR ADC [C]// IEEE APCCAS. Macao, China. 2008: 141-144.

    [5] LEE C, FLYNN M. A SAR-assisted two-stage pipeline ADC [J]. IEEE J Sol Sta Circ, 2011, 46(4): 859-869.

    [6] FURUTA M, NOZAWA M, ITAKURA T. A 10-bit, 40-MS/s, 1.21 mW pipelined SAR ADC using single-ended 1.5-bit/cycle conversion technique [J]. IEEE J Sol Sta Circ, 2011, 46(6): 1360-1370.

    [7] WANG R, CHIO U F, SIN S W,et al. A 12-bit 110 MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique [C]// Proceed ESSCIRC. Bordeaux, France. 2012: 265-268.

    [8] WONG S S, CHIO U F, ZHU Y, et al. A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC [J]. IEEE J Sol Sta Circ, 2013, 48(8): 1783-1794.

    [9] GAO J, LI G, HUANG L,et al. An amplifier-free pipeline-SAR ADC architecture with enhanced speed and energy efficiency [J]. IEEE Trans Circ & Syst II: Expr Bri, 2016, 63(4): 341-345.

    [10] LIU C C, CHANG S J, HUANG G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure [J]. IEEE J Sol Sta Circ, 2010, 45(4): 731-740.

    [11] KUPPAMBATTI J, KINGET P R. A low power zero-crossing pipeline-SAR ADC with on-chip dynamically loaded pre-charged reference [C]// Proceed ESSCIRC. Bucharest, Romania. 2013: 113-116.

    [12] GANDARA M, GUO W, TANG X, et al. A pipelined SAR ADC using the comparator as residue amplifier [C]// IEEE CICC. Austin, TX, USA. 2017: 1-4.

    LI Xiao, LI Xiaoran, ZHANG Hao, YANG Jiaheng, ZHANG Lei. Design of a 10-bit High Speed Pipeline-SAR Hybrid ADC[J]. Microelectronics, 2022, 52(4): 603
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