A 10-bit 100 MS/s pipeline-SAR hybrid ADC without residue amplifier was designed in a 180 nm CMOS process. A two-stage pipeline-SAR hybrid structure was adopted, with the 4-bit most significant bit (MSB) conversion completed in the first stage and the 6-bit least significant bit (LSB) conversion completed in the second stage. In order to reduce the power consumption, the monotonic switching procedure was used, and the residue voltage was delivered from the first stage to the second one by charge sharing. The asynchronous timing control logic was applied to further improve the energy efficiency and the conversion speed. The post-layout simulation results showed that this ADC achieved an ENOB of 9.39 bit and a SNDR of 58.34 dB at 100 MS/s Nyquist sampling rate. The power consumption was 5.9 mW with a 1.8 V supply voltage.