Study on a Lateral Insulated Gate Bipolar Transistor with Surface Superjunction

ZHOU Miao; NI Xiaodong; HE Yitao; CHEN Chen; ZHOU Xin

doi:10.13911/j.cnki.1004-3365.220092

[1] LEUNG Y, PAUL A, PLUMMER J, et al. Lateral IGBT in thin SOI for high voltage, high speed power IC ［J］. IEEE Trans Elec Dev, 1998, 45(10): 2251-2254.

[2] KHO E C T,HOELKE A D, PILKINGTON S J, et al. 200-V lateral superjunction LIGBT on partial SOI ［J］. IEEE Elec Dev Lett, 2012, 33(9): 1291-1293.

[3] ZHU J, ZHANG L, SUN W F, et al. Further study of the u-shaped channel SOI-LIGBT with enhanced current density for high-voltage monolithic ICs ［J］. IEEE Trans Elec Dev, 2016, 63(3):1161-1167.

[4] TRAJKOVIC T, UDUGAMPOLA N, PATHIRANA V, et al. 800 V lateral IGBT in bulk Si for low power compact SMPS applications ［C］// IEEE Int Symp Power Semicond Dev & ICs. Kanazawa, Japan. 2013: 401-404.

[5] SAKURAI N, MORI M, YATSUO T. High speed, high current capacity LIGBT and diode for output stage of high voltage monolithic three-phase inverter IC ［C］// IEEE Int Symp Power Semicond Dev & ICs. Tokyo, Japan. 1990: 66-71.

[6] TEEL E K C, HOLKE A, PILKINGTON S J, et al. A review of techniques used in lateral insulated gate bipolar transistor (LIGBT) ［J］. IOSR J Electrical & Elec Engineer, 2012, 3(1): 35-52.

[7] TSUJIUCHI M, NITTA T, IPPOSHI T, et al. Evolution of 200 V lateral-IGBT technology ［C］// IEEE Int Symp Power Semicond Dev & ICs. Waikoloa, HI, USA, 2014: 426-429.

[8] UDREA F, MILNE W, POPESCU A. Lateral insulated gate bipolar transistor (LIGBT) structure based on partial isolation SOI technology ［J］. Elec Lett, 1997, 33(10): 907-909.

[9] SIMPSON M R. Analysis of negative differential resistance in the I-V characteristics of shorted-anode LIGBT's ［J］. IEEE Trans Elec Dev, 1991, 38(7): 1633-1640.

[10] GARNER D M, UDREA F, LIM HT, et al. An analytic model for turn off in the silicon-on-insulator LIGBT ［J］. Sol Sta Elec, 1999, 43(10): 1855-1868.

[11] SUN W F, ZHU J, ZHANG L, et al. A novel silicon-on-insulator lateral insulated-gate bipolar transistor with dual trenches for three-phase single chip inverter ICs ［J］. IEEE Trans Elec Dev, 2015, 36(7): 693-695.

[13] QIAO M, LI Y F, ZHOU X, et al. A 700-V junction-isolated triple RESURF LDMOS with N-type top layer ［J］. IEEE Elec Dev Lett, 2014, 35(7): 774-776.