[2] ZHANG H, YANG H, ZHANG J, et al. High-speed programmable counter design for PLL based on a delay partition technique [C] // IEEE Int Symp RFIT. Singapore. 2009: 100-103.
[3] BARB G, OTESTANU M. 4G/5G: a comparative study and overview on what to expect from 5G [C] // 43rd Int Conf TSP. Milan, Italy. 2020: 37-40.
[4] ROESSLER A. Impact of spectrum sharing on 4G and 5G standards a review of how coexistance and spectrum sharing is shaping 3GPP standards [C] // IEEE EMCSI. Washington D C, USA. 2017: 704-707.
[6] JIANG P, CHENG M, LU S, et al. A high speed programmable frequency divider [C] // Proceed 3rd IEEE APCAP. Harbin, China. 2014: 1130-1133.
[7] NAN C Z, YU X P, HU B Y, et al. A 6-GHz dual-modulus prescaler using 180 nm SiGe technology [C] // ISIC. Singapore. 2011: 436-439.
[9] SUN Z, XU Y, HU C, et al. Design of novel high speed dual-modulus prescaler based on new optimized structure [C] // IEEE 10th Int Conf ASIC. Shenzhen, China. 2013: 1-4.
[10] ROGERS J, PLETT C, DAI F. Integrated circuit design for high-speed frequency synthesis [M]. Norwood: Artech House, 2006: 177-178.