A High Power Efficient Flash ADC Based on 4 Fold Time-Domain Interpolation

LIU Jianwei; JIANG Junyi; YE Yaqian; YANG Manlin; WANG Peng; WANG Yuxing; FU Xiaojun; LI Ruzhang

doi:10.13911/j.cnki.1004-3365.210225

[1] CHAN C H, ZHU Y, SIN S W, et al. A 5.5 mW 6 b 5 GS/s 4×-interleaved 3 b/cycle SAR ADC in 65 nm CMOS ［C］// ISSCC Dig Tech Pap. San Francisco, CA, USA. 2015: 108-110.

[2] ALPMAN E, LAKDAWALA H, CARLEY L R, et al. A 1.1 V 50 mW 2.5 GS/s 7 b time-interleaved C-2C SAR ADC in 45 nm LP digital CMOS ［C］// ISSCC Dig Tech Pap. San Francisco, CA, USA. 2009: 65-77.

[3] CHAN C H, ZHU Y, SIN S W, et al. A 3.8 mW 8 b 1 GS/s 2 b/cycle interleaving SAR ADC with compact DAC structure ［C］// Dig Symp VLSI Circ. San Francisco, CA, USA. 2012: 86-87.

[4] STEPANOVIC D, NIKOLIC B. A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS ［C］// Dig Symp VLSI Circ. San Francisco, CA, USA. 2012: 84-85.

[5] KIM J I, SUNG B R S, WAN K, et al. A 6-b 4.1 GS/s flash ADC with time-domain latch interpolation in 90-nm CMOS ［J］. IEEE J Sol Sta Circ, 2012, 48(6): 1429-1441.

[6] SHU Y S. A 6 b 3 GS/s 11 mW fully dynamic ADC in 40 nm CMOS with reduced number of comparators ［C］// Symp VLSI Circ. Honolulu, HI, USA. 2012: 26-27.

[7] KIM J I, OH D R, JO D S, et al. A 65 nm CMOS 7 b 2 GS/s 20.7 mW flash ADC with cascaded latch interpolation ［J］. IEEE J Sol Sta Circ, 2015, 50(10): 2319-2330.

[8] CHEN V H C, PILEGGI L. An 8.5 mW 5 GS/s 6 b flash ADC with dynamic offset calibration in 32 nm CMOS SOI ［C］// Symp VLSI Circ. Kyoto, Japan. 2013: 264-265.

[9] MIYAHARA M, MANO I, NAKAYAMA M, et al. A 2.2 GS/s 7 b 27.4 mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers ［C］// ISSCC Dig Tech Pap. San Francisco, CA, USA. 2014: 388-389.

[10] DEGUCHI K, SUWA N, ITO M, et al. A 6-bit 3.5 GS/s 0.9-V 98-mW flash ADC in 90 nm CMOS ［J］. IEEE J Sol Sta Circ, 2008, 43(10): 2303-2310.

[11] WICHT B, NIRSCHL T, SCHMITT-LANDSIEDEL D. Yield and speed optimization of a latch-type voltage sense amplifier ［J］. IEEE J Sol Sta Circ, 2004, 39(7): 1148-1158.

[12] CHAN C H, ZHU Y, SIN S W, et al. A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS ［J］. IEEE J Sol Sta Circ, 2013, 48(9): 2154-2169.

[13] MURMANN B. ADC performance survey 1997-2015 ［EB/OL］. http://web.stanford.edu/~murmann/adcsurvey. html, 2016.