• Microelectronics
  • Vol. 52, Issue 4, 519 (2022)
LIU Jianwei1、2, JIANG Junyi1、2, YE Yaqian1、2, YANG Manlin1、2, WANG Peng1、2, WANG Yuxing1、2, FU Xiaojun1、2, and LI Ruzhang1、2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • show less
    DOI: 10.13911/j.cnki.1004-3365.210225 Cite this Article
    LIU Jianwei, JIANG Junyi, YE Yaqian, YANG Manlin, WANG Peng, WANG Yuxing, FU Xiaojun, LI Ruzhang. A High Power Efficient Flash ADC Based on 4 Fold Time-Domain Interpolation[J]. Microelectronics, 2022, 52(4): 519 Copy Citation Text show less

    Abstract

    A 6-bit 3.4 GS/s flash ADC was designed in a 65 nm CMOS process based on the 4 fold time-domain interpolation technique which allowed the reduction of the number of comparators from the conventional 2N-1 to 2N-2 in a N-bit flash ADC. The proposed scheme achieved effectively a 4 fold interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage, where only offset between the 2N-2 comparators needed to be calibrated. The offset in SR-latches was within ±0.5 LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The prototype achieved 3.4 GS/s sampling frequency with 5.4 bit ENOB at Nyquist and consumed 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/(conv·step).
    LIU Jianwei, JIANG Junyi, YE Yaqian, YANG Manlin, WANG Peng, WANG Yuxing, FU Xiaojun, LI Ruzhang. A High Power Efficient Flash ADC Based on 4 Fold Time-Domain Interpolation[J]. Microelectronics, 2022, 52(4): 519
    Download Citation